mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 00:55:32 +00:00
Refactor +/cmp2lcu.v into recursive techmap
This commit is contained in:
parent
8e851badc4
commit
f68d723cdc
2 changed files with 66 additions and 39 deletions
|
@ -1,5 +1,5 @@
|
|||
read_verilog <<EOT
|
||||
module top(input [11:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
|
||||
module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
|
||||
assign gtu = a > b;
|
||||
assign gts = $signed(a) > $signed(b);
|
||||
assign ltu = a < b;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue