mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-13 16:06:40 +00:00
Fix for Modelsim transcript line warp issue #164
This commit is contained in:
parent
ffcdc53a18
commit
f6221ade95
2 changed files with 17 additions and 11 deletions
|
@ -65,8 +65,8 @@ compile_and_run() {
|
|||
if $use_modelsim; then
|
||||
altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
|
||||
/opt/altera/$altver/modelsim_ase/bin/vlib work
|
||||
/opt/altera/$altver/modelsim_ase/bin/vlog "$@"
|
||||
/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | grep '#OUT#' > "$output"
|
||||
/opt/altera/$altver/modelsim_ase/bin/vlog +define+dmp_name=\"$output\" "$@"
|
||||
/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
|
||||
elif $use_xsim; then
|
||||
(
|
||||
set +x
|
||||
|
@ -76,8 +76,8 @@ compile_and_run() {
|
|||
/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output"
|
||||
)
|
||||
else
|
||||
iverilog -s testbench -o "$exe" "$@"
|
||||
vvp -n "$exe" > "$output"
|
||||
iverilog -Ddmp_name=\"$output\" -s testbench -o "$exe" "$@"
|
||||
vvp -n "$exe"
|
||||
fi
|
||||
}
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue