mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

splitnets: Clean up pseudo-private member usage

Browse source
This commit is contained in:
Alberto Gonzalez 2020-06-13 05:47:55 +00:00
parent b70de98bd1
commit f5d7cd60f5
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 6 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

13
passes/cmds/splitnets.cc
View file

@ -174,12 +174,12 @@ struct SplitnetsPass : public Pass {
std::map<RTLIL::Wire*, std::set<int>> split_wires_at; std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
for (auto &c : module->cells_) for (auto c : module->cells())
for (auto &p : c.second->connections()) for (auto &p : c->connections())
{ {
if (!ct.cell_known(c.second->type)) if (!ct.cell_known(c->type))
continue; continue;
if (!ct.cell_output(c.second->type, p.first)) if (!ct.cell_output(c->type, p.first))
continue; continue;
RTLIL::SigSpec sig = p.second; RTLIL::SigSpec sig = p.second;
@ -206,9 +206,8 @@ struct SplitnetsPass : public Pass {
} }
else else
{ {
for (auto &w : module->wires_) { for (auto wire : module->wires()) {
RTLIL::Wire *wire = w.second; if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
worker.splitmap[wire] = std::vector<RTLIL::SigBit>(); worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
} }