mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-20 14:15:49 +00:00
Code Activity

Bump Yosys to latest

Browse source
This commit is contained in:
Akash Levy 2025-09-13 04:35:52 -07:00
commit f5cb0c328f
153 changed files with 1096 additions and 989 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/techmap/clockgate.cc
View file

@ -81,7 +81,7 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
} else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) {
clk_pol = false;
} else {
log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str());
log("Ignoring ICG primitive %s of kind '%s'\n", cell_name, icg_kind);
continue;
}
@ -176,11 +176,11 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
std::optional<ClockGateCell> pos;
std::optional<ClockGateCell> neg;
if (best_pos) {
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name);
pos.emplace(*best_pos);
}
if (best_neg) {
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name);
neg.emplace(*best_neg);
}
return std::make_pair(pos, neg);