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Bump Yosys to latest

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This commit is contained in:
Akash Levy 2025-09-13 04:35:52 -07:00
commit f5cb0c328f
153 changed files with 1096 additions and 989 deletions
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2
passes/opt/opt_clean.cc
View file

@ -597,7 +597,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
void rmunused_module(RTLIL::Module *module, bool purge_mode, bool unusedbitsattr_mode, bool verbose, bool rminit)
{
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name.c_str());
log("Finding unused cells or wires in module %s..\n", module->name);
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())

2
passes/opt/opt_lut.cc
View file

@ -99,7 +99,7 @@ struct OptLutWorker
}
for (int i = 0; i < GetSize(dlogic); i++)
{
log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type.c_str(), i, dlogic_counts[i]);
log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type, i, dlogic_counts[i]);
}
}

2
passes/opt/opt_merge.cc
View file

@ -228,7 +228,7 @@ struct OptMergeWorker
ct.cell_types.erase(ID($allseq));
ct.cell_types.erase(ID($allconst));
log("Finding identical cells in module `%s'.\n", module->name.c_str());
log("Finding identical cells in module `%s'.\n", module->name);
assign_map.set(module);
initvals.set(&assign_map, module);

2
passes/opt/opt_muxtree.cc
View file

@ -205,7 +205,7 @@ struct OptMuxtreeWorker
OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) :
design(design), module(module), assign_map(module), removed_count(0)
{
log("Running muxtree optimizer on module %s..\n", module->name.c_str());
log("Running muxtree optimizer on module %s..\n", module->name);
log(" Creating internal representation of mux trees.\n");

14
passes/opt/opt_reduce.cc
View file

@ -93,7 +93,7 @@ struct OptReduceWorker
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log_debug(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
log_debug(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
did_something = true;
total_count++;
}
@ -156,7 +156,7 @@ struct OptReduceWorker
}
if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {
log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::B, new_sig_b);
@ -243,7 +243,7 @@ struct OptReduceWorker
}
if (new_sig_s.size() != sig_s.size()) {
log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::A, new_sig_a);
@ -309,7 +309,7 @@ struct OptReduceWorker
if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0)
return;
log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log_debug(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
@ -389,7 +389,7 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log_debug(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
log_debug(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
if (cell->type != ID($bmux)) {
log_debug(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
@ -480,7 +480,7 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log_debug(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
log_debug(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
log_debug(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
@ -516,7 +516,7 @@ struct OptReduceWorker
OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) :
design(design), module(module), assign_map(module)
{
log(" Optimizing cells in module %s.\n", module->name.c_str());
log(" Optimizing cells in module %s.\n", module->name);
total_count = 0;
did_something = true;

10
passes/opt/rmports.cc
View file

@ -64,7 +64,7 @@ struct RmportsPassPass : public Pass {
void CleanupModule(Module *module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Removing now-unused cell ports in module %s\n", module->name.c_str());
log("Removing now-unused cell ports in module %s\n", module->name);
auto cells = module->cells();
for(auto cell : cells)
@ -88,7 +88,7 @@ struct RmportsPassPass : public Pass {
void ScanModule(Module* module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Finding unconnected ports in module %s\n", module->name.c_str());
log("Finding unconnected ports in module %s\n", module->name);
pool<IdString> used_ports;
@ -113,7 +113,7 @@ struct RmportsPassPass : public Pass {
if( (w1 == NULL) || (w2 == NULL) )
continue;
//log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str());
//log(" conn %s, %s\n", w1->name, w2->name);
if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) )
used_ports.insert(w1->name);
@ -136,7 +136,7 @@ struct RmportsPassPass : public Pass {
if(sig == NULL)
continue;
// log(" sig %s\n", sig->name.c_str());
// log(" sig %s\n", sig->name);
if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
used_ports.insert(sig->name);
}
@ -155,7 +155,7 @@ struct RmportsPassPass : public Pass {
// Print the ports out as we go through them
for(auto port : unused_ports)
{
log(" removing unused port %s\n", port.c_str());
log(" removing unused port %s\n", port);
removed_ports[module->name].insert(port);
// Remove from ports list