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	Fixed "opt_const -fine" for $pos cells
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					 1 changed files with 4 additions and 9 deletions
				
			
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					@ -85,7 +85,7 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell
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	did_something = true;
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						did_something = true;
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}
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					}
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static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
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					static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
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{
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					{
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	std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
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						std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
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					@ -96,13 +96,8 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
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	RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name));
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						RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name));
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	RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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						RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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	if (extend_u0) {
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	sig_a.extend_u0(sig_y.size(), a_signed);
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						sig_a.extend_u0(sig_y.size(), a_signed);
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	sig_b.extend_u0(sig_y.size(), b_signed);
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						sig_b.extend_u0(sig_y.size(), b_signed);
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	} else {
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		sig_a.extend(sig_y.size(), a_signed);
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		sig_b.extend(sig_y.size(), b_signed);
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	}
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	std::vector<RTLIL::SigBit> bits_a = sig_a, bits_b = sig_b, bits_y = sig_y;
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						std::vector<RTLIL::SigBit> bits_a = sig_a, bits_b = sig_b, bits_y = sig_y;
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					@ -238,7 +233,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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		{
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							{
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			if (cell->type == "$not" || cell->type == "$pos" ||
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								if (cell->type == "$not" || cell->type == "$pos" ||
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					cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")
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										cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")
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				if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map))
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									if (group_cell_inputs(module, cell, true, assign_map))
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					goto next_cell;
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										goto next_cell;
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			if (cell->type == "$reduce_and")
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								if (cell->type == "$reduce_and")
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