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This commit is contained in:
Eddie Hung 2019-04-11 16:20:43 -07:00
parent b15b410b41
commit f587950bde
1 changed files with 0 additions and 1 deletions
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passes/techmap/pmux2shiftx.cc
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@ -62,7 +62,6 @@ struct Pmux2ShiftxPass : public Pass {
shiftx_a.append(cell->getPort("\\A"));
pmux_s.append(module->Not(NEW_ID, module->ReduceOr(NEW_ID, cell->getPort("\\S"))));
}
const int width = cell->getParam("\\WIDTH").as_int();
const int clog2width = ceil(log2(s_width));
RTLIL::SigSpec pmux_b;