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Merge pull request #3810 from charlottia/docs-celllib-minor

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N. Engelhardt 2023-06-21 10:34:59 +02:00 committed by GitHub
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docs/source/CHAPTER_CellLib.rst
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@ -571,7 +571,7 @@ The ``$mem_v2`` cell has the following ports:
signals for the read ports.
``\RD_DATA``
This input is ``\RD_PORTS*\WIDTH`` bits wide, containing all data
This output is ``\RD_PORTS*\WIDTH`` bits wide, containing all data
signals for the read ports.
``\RD_ARST``