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Added ice40 test_arith

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This commit is contained in:
Clifford Wolf 2015-04-18 09:33:34 +02:00
parent f78fa718be
commit f564a65851
2 changed files with 13 additions and 0 deletions
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10
techlibs/ice40/tests/test_arith.ys Normal file
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read_verilog test_arith.v
synth_ice40
techmap -map ../cells_sim.v
rename test gate
read_verilog test_arith.v
rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter