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verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

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- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
This commit is contained in:
Zachary Snow 2024-02-11 13:28:14 -05:00 • committed by Emil Jiří Tywoniak
parent e8f8297e5d
commit f55fbb5803
6 changed files with 72 additions and 9 deletions
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8
frontends/ast/genrtlil.cc
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@ -2121,11 +2121,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (sig.is_wire()) {
// if the resulting SigSpec is a wire, its
// signedness should match that of the AstNode
if (arg->type == AST_IDENTIFIER && arg->id2ast && arg->id2ast->is_signed && !arg->is_signed)
// fully-sliced signed wire will be resolved
// once the module becomes available
log_assert(attributes.count(ID::reprocess_after));
else
// unless this instantiation depends on module
// information that isn't available yet
if (!attributes.count(ID::reprocess_after))
log_assert(arg->is_signed == sig.as_wire()->is_signed);
} else if (arg->is_signed) {
// non-trivial signed nodes are indirected through