verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.

CHANGELOG

@@ -4,6 +4,11 @@ List of major changes and improvements between releases
 
 Yosys 0.57 .. Yosys 0.58-dev
 --------------------------
+ * Verilog
+    - Fixed an issue that prevented using `{<expr>}` or `$unsigned(<expr>)` for
+      certain signed expressions in port connections
+    - Fixed an issue that prevented writing to a memory word via a concatenation
+      in an output port connection
 
 Yosys 0.56 .. Yosys 0.57
 --------------------------