mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Merge pull request #1258 from YosysHQ/eddie/cleanup

Browse source 
Cleanup a few barnacles across codebase
This commit is contained in:
Clifford Wolf 2019-08-10 09:52:14 +02:00 • committed by GitHub
commit f54bf1631f
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
69 changed files with 405 additions and 414 deletions
Download patch file Download diff file Expand all files Collapse all files

24
passes/techmap/abc.cc
View file

@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig)
void extract_cell(RTLIL::Cell *cell, bool keepff)
{
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
if (clk_polarity != (cell->type == "$_DFF_P_"))
return;
@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
goto matching_dff;
}
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{
if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"))
if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"))
return;
if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"))
if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"))
return;
if (clk_sig != assign_map(cell->getPort("\\C")))
return;
@ -333,17 +333,17 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
{
std::string abc_sname = abc_name.substr(1);
bool isnew = false;
if (abc_sname.substr(0, 4) == "new_")
if (abc_sname.compare(0, 4, "new_") == 0)
{
abc_sname.erase(0, 4);
isnew = true;
}
if (abc_sname.substr(0, 5) == "ys__n")
if (abc_sname.compare(0, 5, "ys__n") == 0)
{
abc_sname.erase(0, 5);
if (std::isdigit(abc_sname.at(0)))
{
int sid = std::stoi(abc_sname);
int sid = std::atoi(abc_sname.c_str());
size_t postfix_start = abc_sname.find_first_not_of("0123456789");
std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : "";
@ -1590,7 +1590,7 @@ struct AbcPass : public Pass {
else if (GetSize(parts) == 1)
lut_costs.push_back(atoi(parts.at(0).c_str()));
else if (GetSize(parts) == 2)
while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
while (GetSize(lut_costs) < std::atoi(parts.at(0).c_str()))
lut_costs.push_back(atoi(parts.at(1).c_str()));
else
log_cmd_error("Invalid -luts syntax.\n");
@ -1861,15 +1861,15 @@ struct AbcPass : public Pass {
}
}
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_"))
{
bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else

10
passes/techmap/abc9.cc
View file

@ -593,7 +593,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
c->setPort("\\Y", module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
}
else if (!lut_costs.empty() || !lut_file.empty()) {
RTLIL::Cell* driver_lut = nullptr;
@ -1153,15 +1153,15 @@ struct Abc9Pass : public Pass {
}
}
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{
bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else

2
passes/techmap/aigmap.cc
View file

@ -66,7 +66,7 @@ struct AigmapPass : public Pass {
{
Aig aig(cell);
if (cell->type == "$_AND_" || cell->type == "$_NOT_")
if (cell->type.in("$_AND_", "$_NOT_"))
aig.name.clear();
if (nand_mode && cell->type == "$_NAND_")

12
passes/techmap/alumacc.cc
View file

@ -315,7 +315,7 @@ struct AlumaccWorker
}
if (subtract_b)
C.append(RTLIL::S1);
C.append(State::S1);
if (GetSize(C) > 1)
goto next_macc;
@ -402,7 +402,7 @@ struct AlumaccWorker
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node;
break;
}
@ -411,7 +411,7 @@ struct AlumaccWorker
n = new alunode_t;
n->a = A;
n->b = B;
n->c = RTLIL::S1;
n->c = State::S1;
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
@ -440,7 +440,7 @@ struct AlumaccWorker
alunode_t *n = nullptr;
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
n = node;
break;
}
@ -484,8 +484,8 @@ struct AlumaccWorker
n->alu_cell->setPort("\\A", n->a);
n->alu_cell->setPort("\\B", n->b);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort("\\Y", n->y);
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y)));

2
passes/techmap/deminout.cc
View file

@ -85,7 +85,7 @@ struct DeminoutPass : public Pass {
if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf"))
{
bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf");
bool tribuf = cell->type.in("$_TBUF_", "$tribuf");
if (!tribuf) {
for (auto &c : cell->connections()) {

14
passes/techmap/dff2dffe.cc
View file

@ -52,13 +52,13 @@ struct Dff2dffeWorker
}
for (auto cell : module->cells()) {
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") {
if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
if (direct_dict.empty()) {
if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_"))
dff_cells.push_back(cell);
} else {
if (direct_dict.count(cell->type))
@ -167,7 +167,7 @@ struct Dff2dffeWorker
}
if (GetSize(or_input) == 0)
return RTLIL::S1;
return State::S1;
if (GetSize(or_input) == 1)
return or_input;
@ -304,7 +304,7 @@ struct Dff2dffePass : public Pass {
}
if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) {
unmap_mode = true;
min_ce_use = std::stoi(args[++argidx]);
min_ce_use = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-direct" && argidx + 2 < args.size()) {
@ -377,7 +377,7 @@ struct Dff2dffePass : public Pass {
mod->remove(cell);
continue;
}
if (cell->type.substr(0, 7) == "$_DFFE_") {
if (cell->type.begins_with("$_DFFE_")) {
if (min_ce_use >= 0) {
int ce_use = 0;
for (auto cell_other : mod->selected_cells()) {
@ -390,8 +390,8 @@ struct Dff2dffePass : public Pass {
continue;
}
bool clk_pol = cell->type.substr(7, 1) == "P";
bool en_pol = cell->type.substr(8, 1) == "P";
bool clk_pol = cell->type.compare(7, 1, "P") == 0;
bool en_pol = cell->type.compare(8, 1, "P") == 0;
RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol);
if (en_pol)

10
passes/techmap/extract.cc
View file

@ -54,7 +54,7 @@ public:
RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value)
{
if (cell_type.substr(0, 1) != "$" || cell_type.substr(0, 2) == "$_")
if (!cell_type.begins_with("$") || cell_type.begins_with("$_"))
return value;
#define param_bool(_n) if (param == _n) return value.as_bool();
@ -203,7 +203,7 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
continue;
std::string type = cell->type.str();
if (sel == NULL && type.substr(0, 2) == "\\$")
if (sel == NULL && type.compare(0, 2, "\\$") == 0)
type = type.substr(1);
graph.createNode(cell->name.str(), type, (void*)cell);
@ -594,7 +594,7 @@ struct ExtractPass : public Pass {
map = new RTLIL::Design;
for (auto &filename : map_filenames)
{
if (filename.substr(0, 1) == "%")
if (filename.compare(0, 1, "%") == 0)
{
if (!saved_designs.count(filename.substr(1))) {
delete map;
@ -613,10 +613,10 @@ struct ExtractPass : public Pass {
delete map;
log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
}
Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
f.close();
if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) {
Pass::call(map, "proc");
Pass::call(map, "opt_clean");
}

16
passes/techmap/maccmap.cc
View file

@ -36,7 +36,7 @@ struct MaccmapWorker
void add(RTLIL::SigBit bit, int position)
{
if (position >= width || bit == RTLIL::S0)
if (position >= width || bit == State::S0)
return;
if (bits.at(position).count(bit)) {
@ -53,7 +53,7 @@ struct MaccmapWorker
if (do_subtract) {
a = module->Not(NEW_ID, a);
add(RTLIL::S1, 0);
add(State::S1, 0);
}
for (int i = 0; i < width; i++)
@ -80,7 +80,7 @@ struct MaccmapWorker
else
{
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {a.extract(0, width-1), RTLIL::S0};
a = {a.extract(0, width-1), State::S0};
}
}
@ -88,10 +88,10 @@ struct MaccmapWorker
{
int start_index = 0, stop_index = GetSize(in1);
while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
while (start_index < stop_index && in1[start_index] == State::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
start_index++;
while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
while (start_index < stop_index && in1[stop_index-1] == State::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
stop_index--;
if (start_index == stop_index)
@ -222,7 +222,7 @@ struct MaccmapWorker
RTLIL::SigSpec in3 = summands[i+2];
RTLIL::SigSpec out1, out2;
fulladd(in1, in2, in3, out1, out2);
RTLIL::SigBit extra_bit = RTLIL::S0;
RTLIL::SigBit extra_bit = State::S0;
if (!tree_sum_bits.empty()) {
extra_bit = tree_sum_bits.back();
tree_sum_bits.pop_back();
@ -240,8 +240,8 @@ struct MaccmapWorker
RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
c->setPort("\\A", summands.front());
c->setPort("\\B", summands.back());
c->setPort("\\CI", RTLIL::S0);
c->setPort("\\BI", RTLIL::S0);
c->setPort("\\CI", State::S0);
c->setPort("\\BI", State::S0);
c->setPort("\\Y", module->addWire(NEW_ID, width));
c->setPort("\\X", module->addWire(NEW_ID, width));
c->setPort("\\CO", module->addWire(NEW_ID, width));

20
passes/techmap/muxcover.cc
View file

@ -675,36 +675,36 @@ struct MuxcoverPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++)
{
const auto &arg = args[argidx];
if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") {
cost_mux2 = std::stoi(arg.substr(6));
if (arg.size() >= 6 && arg.compare(0,6,"-mux2=") == 0) {
cost_mux2 = atoi(arg.substr(6).c_str());
continue;
}
if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") {
if (arg.size() >= 5 && arg.compare(0,5,"-mux4") == 0) {
use_mux4 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
cost_mux4 = std::stoi(arg.substr(6));
cost_mux4 = atoi(arg.substr(6).c_str());
}
continue;
}
if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") {
if (arg.size() >= 5 && arg.compare(0,5,"-mux8") == 0) {
use_mux8 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
cost_mux8 = std::stoi(arg.substr(6));
cost_mux8 = atoi(arg.substr(6).c_str());
}
continue;
}
if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") {
if (arg.size() >= 6 && arg.compare(0,6,"-mux16") == 0) {
use_mux16 = true;
if (arg.size() > 6) {
if (arg[6] != '=') break;
cost_mux16 = std::stoi(arg.substr(7));
cost_mux16 = atoi(arg.substr(7).c_str());
}
continue;
}
if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") {
cost_dmux = std::stoi(arg.substr(6));
if (arg.size() >= 6 && arg.compare(0,6,"-dmux=") == 0) {
cost_dmux = atoi(arg.substr(6).c_str());
continue;
}
if (arg == "-nodecode") {

4
passes/techmap/simplemap.cc
View file

@ -185,7 +185,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
}
if (sig.size() == 0)
sig = RTLIL::SigSpec(0, 1);
sig = State::S0;
}
void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
bool is_ne = cell->type == "$ne" || cell->type == "$nex";
bool is_ne = cell->type.in("$ne", "$nex");
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);

20
passes/techmap/techmap.cc
View file

@ -243,7 +243,7 @@ struct TechmapWorker
if (positional_ports.count(portname) > 0)
portname = positional_ports.at(portname);
if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
if (portname.substr(0, 1) == "$")
if (portname.begins_with("$"))
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
continue;
}
@ -341,7 +341,7 @@ struct TechmapWorker
RTLIL::Cell *c = module->addCell(c_name, it.second);
design->select(module, c);
if (!flatten_mode && c->type.substr(0, 2) == "\\$")
if (!flatten_mode && c->type.begins_with("\\$"))
c->type = c->type.substr(1);
for (auto &it2 : c->connections_) {
@ -406,7 +406,7 @@ struct TechmapWorker
continue;
std::string cell_type = cell->type.str();
if (in_recursion && cell_type.substr(0, 2) == "\\$")
if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
if (celltypeMap.count(cell_type) == 0) {
@ -468,7 +468,7 @@ struct TechmapWorker
std::string cell_type = cell->type.str();
if (in_recursion && cell_type.substr(0, 2) == "\\$")
if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
for (auto &tpl_name : celltypeMap.at(cell_type))
@ -602,7 +602,7 @@ struct TechmapWorker
}
for (auto conn : cell->connections()) {
if (conn.first.substr(0, 1) == "$")
if (conn.first.begins_with("$"))
continue;
if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
continue;
@ -725,7 +725,7 @@ struct TechmapWorker
for (auto &it : twd)
{
if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
continue;
auto &data = it.second.front();
@ -874,7 +874,7 @@ struct TechmapWorker
tpl->cloneInto(m);
for (auto cell : m->cells()) {
if (cell->type.substr(0, 2) == "\\$")
if (cell->type.begins_with("\\$"))
cell->type = cell->type.substr(1);
}
@ -1113,7 +1113,7 @@ struct TechmapPass : public Pass {
Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
} else {
for (auto &fn : map_files)
if (fn.substr(0, 1) == "%") {
if (fn.compare(0, 1, "%") == 0) {
if (!saved_designs.count(fn.substr(1))) {
delete map;
log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
@ -1128,7 +1128,7 @@ struct TechmapPass : public Pass {
yosys_input_files.insert(fn);
if (f.fail())
log_cmd_error("Can't open map file `%s'\n", fn.c_str());
Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
}
}
@ -1143,7 +1143,7 @@ struct TechmapPass : public Pass {
free(p);
} else {
string module_name = it.first.str();
if (module_name.substr(0, 2) == "\\$")
if (it.first.begins_with("\\$"))
module_name = module_name.substr(1);
celltypeMap[module_name].insert(it.first);
}