mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Code Activity

CMake: initial work

Browse source
This commit is contained in:
Miodrag Milanovic 2025-02-12 14:18:02 +01:00
parent df3c62a4ed
commit f51a2d793a
19 changed files with 430 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

46
frontends/verilog/CMakeLists.txt Normal file
View file

@ -0,0 +1,46 @@
#add_custom_command(
# COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}
# OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.cc ${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.hh
# COMMAND ${BISON_EXECUTABLE}
# -Wall -Werror
# -o verilog_parser.tab.cc
# -d -r all
# ${CMAKE_CURRENT_SOURCE_DIR}/verilog_parser.y
# DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/verilog_parser.y
# COMMENT "Generating frontends/verilog/verilog_parser.tab.cc"
# VERBATIM
# COMMAND_EXPAND_LISTS
#)
#
#add_custom_command(
# COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}
# OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/verilog_lexer.cc
# COMMAND ${FLEX_EXECUTABLE}
# --outfile=verilog_lexer.cc
# ${CMAKE_CURRENT_SOURCE_DIR}/verilog_lexer.l
# DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/verilog_lexer.l
# COMMENT "Generating frontends/verilog/verilog_lexer.cc"
# VERBATIM
# COMMAND_EXPAND_LISTS
#)
flex_target(VERILOG_LEXER "verilog_lexer.l" "${CMAKE_CURRENT_BINARY_DIR}/verilog_lexer.cc")
bison_target(VERILOG_PARSER "verilog_parser.y" "${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.cc" DEFINES_FILE "${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.hh" COMPILE_FLAGS "-Wall -Werror -d -r all")
add_library(yosys_frontends_verilog INTERFACE)
target_sources(yosys_frontends_verilog INTERFACE
const2ast.cc
preproc.cc
preproc.h
verilog_frontend.cc
verilog_frontend.h
)
add_library(yosys_frontends_verilog_gen OBJECT
${FLEX_VERILOG_LEXER_OUTPUTS}
${BISON_VERILOG_PARSER_OUTPUTS}
#${CMAKE_CURRENT_BINARY_DIR}/verilog_lexer.cc
#${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.cc
#${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.hh
)
target_link_libraries(yosys PRIVATE yosys_frontends_verilog yosys_frontends_verilog_gen)