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frontend: Make helper functions for printing locations.

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This commit is contained in:
Marcelina Kościelnicka 2021-02-23 19:22:53 +01:00
parent ad2960adb7
commit f4f471f342
4 changed files with 71 additions and 57 deletions
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24
frontends/ast/ast.cc
View file

@ -287,8 +287,7 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
} }
std::string type_name = type2str(type); std::string type_name = type2str(type);
fprintf(f, "%s%s <%s:%d.%d-%d.%d>", indent.c_str(), type_name.c_str(), filename.c_str(), location.first_line, fprintf(f, "%s%s <%s>", indent.c_str(), type_name.c_str(), loc_string().c_str());
location.first_column, location.last_line, location.last_column);
if (!flag_no_dump_ptr) { if (!flag_no_dump_ptr) {
if (id2ast) if (id2ast)
@ -959,6 +958,16 @@ RTLIL::Const AstNode::realAsConst(int width)
return result; return result;
} }
std::string AstNode::loc_string() const
{
return stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
}
void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
{
obj->attributes[ID::src] = ast->loc_string();
}
// create a new AstModule from an AST_MODULE AST node // create a new AstModule from an AST_MODULE AST node
static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false) static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
{ {
@ -974,8 +983,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
current_module = new AstModule; current_module = new AstModule;
current_module->ast = NULL; current_module->ast = NULL;
current_module->name = ast->str; current_module->name = ast->str;
current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, set_src_attr(current_module, ast);
ast->location.first_column, ast->location.last_line, ast->location.last_column);
current_module->set_bool_attribute(ID::cells_not_processed); current_module->set_bool_attribute(ID::cells_not_processed);
current_ast_mod = ast; current_ast_mod = ast;
@ -1229,13 +1237,13 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
log_file_error((*it)->filename, (*it)->location.first_line, "Re-definition of module `%s'!\n", (*it)->str.c_str()); log_file_error((*it)->filename, (*it)->location.first_line, "Re-definition of module `%s'!\n", (*it)->str.c_str());
} else if (nooverwrite) { } else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s:%d.%d-%d.%d.\n", log("Ignoring re-definition of module `%s' at %s.\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column); (*it)->str.c_str(), (*it)->loc_string().c_str());
continue; continue;
} else { } else {
log("Replacing existing%s module `%s' at %s:%d.%d-%d.%d.\n", log("Replacing existing%s module `%s' at %s.\n",
existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column); (*it)->str.c_str(), (*it)->loc_string().c_str());
design->remove(existing_mod); design->remove(existing_mod);
} }
} }

6
frontends/ast/ast.h
View file

@ -323,6 +323,9 @@ namespace AST
// helpers for enum // helpers for enum
void allocateDefaultEnumValues(); void allocateDefaultEnumValues();
void annotateTypedEnums(AstNode *template_node); void annotateTypedEnums(AstNode *template_node);
// helpers for locations
std::string loc_string() const;
}; };
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
@ -361,6 +364,9 @@ namespace AST
std::pair<std::string,std::string> split_modport_from_type(std::string name_type); std::pair<std::string,std::string> split_modport_from_type(std::string name_type);
AstNode * find_modport(AstNode *intf, std::string name); AstNode * find_modport(AstNode *intf, std::string name);
void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport); void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);
// Helper for setting the src attribute.
void set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast);
} }
namespace AST_INTERNAL namespace AST_INTERNAL

50
frontends/ast/genrtlil.cc
View file

@ -45,10 +45,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width
{ {
IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++); IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, type); RTLIL::Cell *cell = current_module->addCell(name, type);
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(wire, that);
wire->is_signed = that->is_signed; wire->is_signed = that->is_signed;
if (gen_attributes) if (gen_attributes)
@ -77,10 +77,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++); IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, ID($pos)); RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(wire, that);
wire->is_signed = that->is_signed; wire->is_signed = that->is_signed;
if (that != NULL) if (that != NULL)
@ -104,10 +104,10 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width
{ {
IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++); IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, type); RTLIL::Cell *cell = current_module->addCell(name, type);
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(wire, that);
wire->is_signed = that->is_signed; wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) { for (auto &attr : that->attributes) {
@ -139,10 +139,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux)); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); set_src_attr(wire, that);
wire->is_signed = that->is_signed; wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) { for (auto &attr : that->attributes) {
@ -320,7 +320,7 @@ struct AST_INTERNAL::ProcessGenerator
// generate process and simple root case // generate process and simple root case
proc = new RTLIL::Process; proc = new RTLIL::Process;
proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); set_src_attr(proc, always);
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++); proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
for (auto &attr : always->attributes) { for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
@ -356,7 +356,7 @@ struct AST_INTERNAL::ProcessGenerator
if (found_anyedge_syncs) { if (found_anyedge_syncs) {
if (found_global_syncs) if (found_global_syncs)
log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n"); log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
log("Note: Assuming pure combinatorial block at %s:%d.%d-%d.%d in\n", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str());
log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n"); log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
log("use of @* instead of @(...) for better match of synthesis and simulation.\n"); log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
} }
@ -456,7 +456,7 @@ struct AST_INTERNAL::ProcessGenerator
} while (current_module->wires_.count(wire_name) > 0); } while (current_module->wires_.count(wire_name) > 0);
RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width); RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); set_src_attr(wire, always);
chunk.wire = wire; chunk.wire = wire;
chunk.offset = 0; chunk.offset = 0;
@ -591,7 +591,7 @@ struct AST_INTERNAL::ProcessGenerator
case AST_CASE: case AST_CASE:
{ {
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column); set_src_attr(sw, ast);
sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap()); sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
current_case->switches.push_back(sw); current_case->switches.push_back(sw);
@ -625,7 +625,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::CaseRule *backup_case = current_case; RTLIL::CaseRule *backup_case = current_case;
current_case = new RTLIL::CaseRule; current_case = new RTLIL::CaseRule;
current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column); set_src_attr(current_case, child);
last_generated_case = current_case; last_generated_case = current_case;
addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue); addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
for (auto node : child->children) { for (auto node : child->children) {
@ -1048,7 +1048,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// This is used by the hierarchy pass to know when it can replace interface connection with the individual // This is used by the hierarchy pass to know when it can replace interface connection with the individual
// signals. // signals.
RTLIL::Wire *wire = current_module->addWire(str, 1); RTLIL::Wire *wire = current_module->addWire(str, 1);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(wire, this);
wire->start_offset = 0; wire->start_offset = 0;
wire->port_id = port_id; wire->port_id = port_id;
wire->port_input = true; wire->port_input = true;
@ -1089,7 +1089,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
current_module->connect(wire, val); current_module->connect(wire, val);
wire->is_signed = children[0]->is_signed; wire->is_signed = children[0]->is_signed;
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(wire, this);
wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1; wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1;
for (auto &attr : attributes) { for (auto &attr : attributes) {
@ -1111,7 +1111,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(wire, this);
wire->start_offset = range_right; wire->start_offset = range_right;
wire->port_id = port_id; wire->port_id = port_id;
wire->port_input = is_input; wire->port_input = is_input;
@ -1143,7 +1143,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str()); log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
RTLIL::Memory *memory = new RTLIL::Memory; RTLIL::Memory *memory = new RTLIL::Memory;
memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(memory, this);
memory->name = str; memory->name = str;
memory->width = children[0]->range_left - children[0]->range_right + 1; memory->width = children[0]->range_left - children[0]->range_right + 1;
if (children[1]->range_right < children[1]->range_left) { if (children[1]->range_right < children[1]->range_left) {
@ -1200,7 +1200,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) { if (id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
RTLIL::Wire *wire = current_module->addWire(str); RTLIL::Wire *wire = current_module->addWire(str);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(wire, this);
wire->name = str; wire->name = str;
if (flag_autowire) if (flag_autowire)
log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str()); log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
@ -1582,10 +1582,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd)); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(cell, this);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(wire, this);
int mem_width, mem_size, addr_bits; int mem_width, mem_size, addr_bits;
is_signed = id2ast->is_signed; is_signed = id2ast->is_signed;
@ -1621,7 +1621,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit)); RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(cell, this);
int mem_width, mem_size, addr_bits; int mem_width, mem_size, addr_bits;
id2ast->meminfo(mem_width, mem_size, addr_bits); id2ast->meminfo(mem_width, mem_size, addr_bits);
@ -1685,7 +1685,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cellname = str; cellname = str;
RTLIL::Cell *cell = current_module->addCell(cellname, celltype); RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(cell, this);
for (auto &attr : attributes) { for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
@ -1730,7 +1730,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str()); log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
RTLIL::Cell *cell = current_module->addCell(str, ""); RTLIL::Cell *cell = current_module->addCell(str, "");
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(cell, this);
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
cell->set_bool_attribute(ID::module_not_derived); cell->set_bool_attribute(ID::module_not_derived);
@ -1894,7 +1894,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
Cell *cell = current_module->addCell(myid, str.substr(1)); Cell *cell = current_module->addCell(myid, str.substr(1));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(cell, this);
cell->parameters[ID::WIDTH] = width; cell->parameters[ID::WIDTH] = width;
if (attributes.count(ID::reg)) { if (attributes.count(ID::reg)) {
@ -1905,7 +1905,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
Wire *wire = current_module->addWire(myid + "_wire", width); Wire *wire = current_module->addWire(myid + "_wire", width);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); set_src_attr(wire, this);
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
is_signed = sign_hint; is_signed = sign_hint;

48
frontends/ast/simplify.cc
View file

@ -943,7 +943,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic) if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg) if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
log_warning("wire '%s' is assigned in a block at %s:%d.%d-%d.%d.\n", children[0]->str.c_str(), filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); log_warning("wire '%s' is assigned in a block at %s.\n", children[0]->str.c_str(), loc_string().c_str());
if (type == AST_ASSIGN && children[0]->id2ast->is_reg) { if (type == AST_ASSIGN && children[0]->id2ast->is_reg) {
bool is_rand_reg = false; bool is_rand_reg = false;
if (children[1]->type == AST_FCALL) { if (children[1]->type == AST_FCALL) {
@ -957,7 +957,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
is_rand_reg = true; is_rand_reg = true;
} }
if (!is_rand_reg) if (!is_rand_reg)
log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.%d-%d.%d.\n", children[0]->str.c_str(), filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); log_warning("reg '%s' is assigned in a continuous assignment at %s.\n", children[0]->str.c_str(), loc_string().c_str());
} }
children[0]->was_checked = true; children[0]->was_checked = true;
} }
@ -4541,8 +4541,8 @@ bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
if (children.size() != 1 || children.at(0)->type != AST_RANGE) { if (children.size() != 1 || children.at(0)->type != AST_RANGE) {
if (!must_succeed) if (!must_succeed)
return false; return false;
log_file_error(filename, location.first_line, "Memory access in constant function is not supported\n%s:%d.%d-%d.%d: ...called from here.\n", log_file_error(filename, location.first_line, "Memory access in constant function is not supported\n%s: ...called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
if (!children.at(0)->replace_variables(variables, fcall, must_succeed)) if (!children.at(0)->replace_variables(variables, fcall, must_succeed))
return false; return false;
@ -4550,8 +4550,8 @@ bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
if (!children.at(0)->range_valid) { if (!children.at(0)->range_valid) {
if (!must_succeed) if (!must_succeed)
return false; return false;
log_file_error(filename, location.first_line, "Non-constant range\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(filename, location.first_line, "Non-constant range\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
offset = min(children.at(0)->range_left, children.at(0)->range_right); offset = min(children.at(0)->range_left, children.at(0)->range_right);
width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width); width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
@ -4602,8 +4602,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
if (!stmt->range_valid) { if (!stmt->range_valid) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Can't determine size of variable %s\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(stmt->filename, stmt->location.first_line, "Can't determine size of variable %s\n%s: ... called from here.\n",
stmt->str.c_str(), fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); stmt->str.c_str(), fcall->loc_string().c_str());
} }
AstNode::varinfo_t &variable = variables[stmt->str]; AstNode::varinfo_t &variable = variables[stmt->str];
int width = abs(stmt->range_left - stmt->range_right) + 1; int width = abs(stmt->range_left - stmt->range_right) + 1;
@ -4664,22 +4664,22 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
if (stmt->children.at(1)->type != AST_CONSTANT) { if (stmt->children.at(1)->type != AST_CONSTANT) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here. X\n", log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here. X\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
if (stmt->children.at(0)->type != AST_IDENTIFIER) { if (stmt->children.at(0)->type != AST_IDENTIFIER) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Unsupported composite left hand side in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(stmt->filename, stmt->location.first_line, "Unsupported composite left hand side in constant function\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
if (!variables.count(stmt->children.at(0)->str)) { if (!variables.count(stmt->children.at(0)->str)) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Assignment to non-local variable in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(stmt->filename, stmt->location.first_line, "Assignment to non-local variable in constant function\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
if (stmt->children.at(0)->children.empty()) { if (stmt->children.at(0)->children.empty()) {
@ -4689,8 +4689,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
if (!range->range_valid) { if (!range->range_valid) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(range->filename, range->location.first_line, "Non-constant range\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(range->filename, range->location.first_line, "Non-constant range\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
int offset = min(range->range_left, range->range_right); int offset = min(range->range_left, range->range_right);
int width = std::abs(range->range_left - range->range_right) + 1; int width = std::abs(range->range_left - range->range_right) + 1;
@ -4725,8 +4725,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
if (cond->type != AST_CONSTANT) { if (cond->type != AST_CONSTANT) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
if (cond->asBool()) { if (cond->asBool()) {
@ -4750,8 +4750,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
if (num->type != AST_CONSTANT) { if (num->type != AST_CONSTANT) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
block->children.erase(block->children.begin()); block->children.erase(block->children.begin());
@ -4793,8 +4793,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
if (cond->type != AST_CONSTANT) { if (cond->type != AST_CONSTANT) {
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
} }
found_match = cond->asBool(); found_match = cond->asBool();
@ -4829,8 +4829,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
if (!must_succeed) if (!must_succeed)
goto finished; goto finished;
log_file_error(stmt->filename, stmt->location.first_line, "Unsupported language construct in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", log_file_error(stmt->filename, stmt->location.first_line, "Unsupported language construct in constant function\n%s: ... called from here.\n",
fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); fcall->loc_string().c_str());
log_abort(); log_abort();
} }