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Add clock buffer insertion pass, improve iopadmap.

A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
This commit is contained in:
Marcin Kościelnicki 2019-08-12 15:57:43 +00:00
parent 78b30bbb11
commit f4c62f33ac
10 changed files with 577 additions and 93 deletions

View file

@ -63,6 +63,9 @@ struct SynthXilinxPass : public ScriptPass
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
log(" -ise\n");
log(" generate an output netlist suitable for ISE\n");
log("\n");
log(" -nobram\n");
log(" disable inference of block rams\n");
log("\n");
@ -78,6 +81,12 @@ struct SynthXilinxPass : public ScriptPass
log(" -nowidelut\n");
log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
log("\n");
log(" -iopads\n");
log(" perform I/O buffer insertion (selected automatically by -ise)\n");
log("\n");
log(" -noiopads\n");
log(" disable I/O buffer insertion (only useful with -ise)\n");
log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
@ -104,7 +113,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
int widemux;
void clear_flags() YS_OVERRIDE
@ -116,6 +125,9 @@ struct SynthXilinxPass : public ScriptPass
flatten = false;
retime = false;
vpr = false;
ise = false;
iopads = false;
noiopads = false;
nocarry = false;
nobram = false;
nodram = false;
@ -178,6 +190,18 @@ struct SynthXilinxPass : public ScriptPass
vpr = true;
continue;
}
if (args[argidx] == "-ise") {
ise = true;
continue;
}
if (args[argidx] == "-iopads") {
iopads = true;
continue;
}
if (args[argidx] == "-noiopads") {
noiopads = true;
continue;
}
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
@ -410,6 +434,17 @@ struct SynthXilinxPass : public ScriptPass
run("clean");
}
if (check_label("finalize")) {
bool do_iopads = iopads || (ise && !noiopads);
if (help_mode || do_iopads)
run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')");
else
run("clkbufmap -buf BUFG O:I");
if (do_iopads)
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')");
}
if (check_label("check")) {
run("hierarchy -check");
run("stat -tech xilinx");