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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
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10 changed files with 577 additions and 93 deletions
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@ -63,6 +63,9 @@ struct SynthXilinxPass : public ScriptPass
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log(" -ise\n");
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log(" generate an output netlist suitable for ISE\n");
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log("\n");
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log(" -nobram\n");
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log(" disable inference of block rams\n");
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log("\n");
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@ -78,6 +81,12 @@ struct SynthXilinxPass : public ScriptPass
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log(" -nowidelut\n");
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log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
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log("\n");
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log(" -iopads\n");
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log(" perform I/O buffer insertion (selected automatically by -ise)\n");
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log("\n");
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log(" -noiopads\n");
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log(" disable I/O buffer insertion (only useful with -ise)\n");
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log("\n");
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log(" -widemux <int>\n");
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log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
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log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
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@ -104,7 +113,7 @@ struct SynthXilinxPass : public ScriptPass
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}
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std::string top_opt, edif_file, blif_file, family;
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bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
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bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
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int widemux;
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void clear_flags() YS_OVERRIDE
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@ -116,6 +125,9 @@ struct SynthXilinxPass : public ScriptPass
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flatten = false;
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retime = false;
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vpr = false;
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ise = false;
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iopads = false;
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noiopads = false;
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nocarry = false;
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nobram = false;
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nodram = false;
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@ -178,6 +190,18 @@ struct SynthXilinxPass : public ScriptPass
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vpr = true;
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continue;
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}
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if (args[argidx] == "-ise") {
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ise = true;
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continue;
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}
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if (args[argidx] == "-iopads") {
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iopads = true;
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continue;
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}
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if (args[argidx] == "-noiopads") {
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noiopads = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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nocarry = true;
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continue;
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@ -410,6 +434,17 @@ struct SynthXilinxPass : public ScriptPass
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run("clean");
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}
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if (check_label("finalize")) {
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bool do_iopads = iopads || (ise && !noiopads);
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if (help_mode || do_iopads)
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run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')");
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else
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run("clkbufmap -buf BUFG O:I");
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if (do_iopads)
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run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')");
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}
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if (check_label("check")) {
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run("hierarchy -check");
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run("stat -tech xilinx");
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