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https://github.com/YosysHQ/yosys
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
This commit is contained in:
Marcin Kościelnicki
parent
78b30bbb11
commit
f4c62f33ac
10 changed files with 577 additions and 93 deletions
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@ -1,5 +1,6 @@
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// Created by cells_xtra.sh from Xilinx models
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(* keep *)
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module BSCANE2 (...);
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parameter DISABLE_JTAG = "FALSE";
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parameter integer JTAG_CHAIN = 1;
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@ -16,6 +17,7 @@ module BSCANE2 (...);
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input TDO;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFGCE (...);
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parameter CE_TYPE = "SYNC";
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parameter [0:0] IS_CE_INVERTED = 1'b0;
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@ -25,23 +27,28 @@ module BUFGCE (...);
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input I;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFGCE_1 (...);
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output O;
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input CE, I;
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input CE;
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input I;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFGMUX (...);
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parameter CLK_SEL_TYPE = "SYNC";
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output O;
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input I0, I1, S;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFGMUX_1 (...);
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parameter CLK_SEL_TYPE = "SYNC";
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output O;
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input I0, I1, S;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFGMUX_CTRL (...);
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output O;
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input I0;
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@ -49,21 +56,25 @@ module BUFGMUX_CTRL (...);
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input S;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFH (...);
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output O;
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input I;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFIO (...);
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output O;
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input I;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFMR (...);
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output O;
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input I;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFMRCE (...);
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parameter CE_TYPE = "SYNC";
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parameter integer INIT_OUT = 0;
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@ -73,6 +84,7 @@ module BUFMRCE (...);
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input I;
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endmodule
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(* clkbuf_driver = "O" *)
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module BUFR (...);
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output O;
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input CE;
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@ -89,6 +101,7 @@ module CAPTUREE2 (...);
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input CLK;
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endmodule
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(* clkbuf_sink = "CLK" *)
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module CFGLUT5 (...);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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@ -111,6 +124,7 @@ module DNA_PORT (...);
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input CLK, DIN, READ, SHIFT;
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endmodule
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(* clkbuf_sink = "CLK" *)
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module DSP48E1 (...);
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parameter integer ACASCREG = 1;
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parameter integer ADREG = 1;
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@ -198,6 +212,7 @@ module EFUSE_USR (...);
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output [31:0] EFUSEUSR;
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endmodule
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(* clkbuf_sink = "RDCLK,WRCLK" *)
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module FIFO18E1 (...);
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parameter ALMOST_EMPTY_OFFSET = 13'h0080;
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parameter ALMOST_FULL_OFFSET = 13'h0080;
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@ -236,6 +251,7 @@ module FIFO18E1 (...);
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input WREN;
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endmodule
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(* clkbuf_sink = "RDCLK,WRCLK" *)
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module FIFO36E1 (...);
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parameter ALMOST_EMPTY_OFFSET = 13'h0080;
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parameter ALMOST_FULL_OFFSET = 13'h0080;
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@ -1963,6 +1979,7 @@ module GTXE2_COMMON (...);
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input [7:0] PMARSVD;
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endmodule
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(* iopad_external_pin = "I" *)
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module IBUF_IBUFDISABLE (...);
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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@ -1973,6 +1990,7 @@ module IBUF_IBUFDISABLE (...);
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input IBUFDISABLE;
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endmodule
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(* iopad_external_pin = "I" *)
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module IBUF_INTERMDISABLE (...);
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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@ -1984,6 +2002,7 @@ module IBUF_INTERMDISABLE (...);
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input INTERMDISABLE;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFDS (...);
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parameter CAPACITANCE = "DONT_CARE";
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parameter DIFF_TERM = "FALSE";
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@ -1996,6 +2015,7 @@ module IBUFDS (...);
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input I, IB;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFDS_DIFF_OUT (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2005,6 +2025,7 @@ module IBUFDS_DIFF_OUT (...);
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input I, IB;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2019,6 +2040,7 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
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input IBUFDISABLE;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2034,6 +2056,7 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
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input INTERMDISABLE;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFDS_GTE2 (...);
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parameter CLKCM_CFG = "TRUE";
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parameter CLKRCV_TRST = "TRUE";
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@ -2045,6 +2068,7 @@ module IBUFDS_GTE2 (...);
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input IB;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFDS_IBUFDISABLE (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2058,6 +2082,7 @@ module IBUFDS_IBUFDISABLE (...);
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input IBUFDISABLE;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFDS_INTERMDISABLE (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2072,6 +2097,37 @@ module IBUFDS_INTERMDISABLE (...);
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input INTERMDISABLE;
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endmodule
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(* iopad_external_pin = "I" *)
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module IBUFG (...);
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parameter CAPACITANCE = "DONT_CARE";
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parameter IBUF_DELAY_VALUE = "0";
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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output O;
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input I;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFGDS (...);
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parameter CAPACITANCE = "DONT_CARE";
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parameter DIFF_TERM = "FALSE";
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parameter IBUF_DELAY_VALUE = "0";
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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output O;
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input I, IB;
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endmodule
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(* iopad_external_pin = "I,IB" *)
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module IBUFGDS_DIFF_OUT (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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output O, OB;
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input I, IB;
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endmodule
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(* keep *)
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module ICAPE2 (...);
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parameter [31:0] DEVICE_ID = 32'h04244093;
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@ -2084,6 +2140,7 @@ module ICAPE2 (...);
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input [31:0] I;
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endmodule
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(* clkbuf_sink = "C" *)
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module IDDR (...);
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parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
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parameter INIT_Q1 = 1'b0;
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@ -2102,6 +2159,7 @@ module IDDR (...);
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input S;
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endmodule
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(* clkbuf_sink = "C,CB" *)
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module IDDR_2CLK (...);
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parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
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parameter INIT_Q1 = 1'b0;
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@ -2120,7 +2178,7 @@ module IDDR_2CLK (...);
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input S;
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endmodule
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(* keep *)
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(* keep *) (* clkbuf_sink = "REFCLK" *)
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module IDELAYCTRL (...);
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parameter SIM_DEVICE = "7SERIES";
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output RDY;
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@ -2128,6 +2186,7 @@ module IDELAYCTRL (...);
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input RST;
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endmodule
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(* clkbuf_sink = "C" *)
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module IDELAYE2 (...);
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parameter CINVCTRL_SEL = "FALSE";
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parameter DELAY_SRC = "IDATAIN";
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@ -2155,6 +2214,7 @@ module IDELAYE2 (...);
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input REGRST;
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endmodule
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(* clkbuf_sink = "RDCLK,WRCLK" *)
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module IN_FIFO (...);
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parameter integer ALMOST_EMPTY_VALUE = 1;
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parameter integer ALMOST_FULL_VALUE = 1;
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@ -2191,6 +2251,7 @@ module IN_FIFO (...);
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input [7:0] D6;
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endmodule
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(* iopad_external_pin = "IO" *)
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module IOBUF (...);
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parameter integer DRIVE = 12;
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parameter IBUF_LOW_PWR = "TRUE";
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@ -2201,6 +2262,7 @@ module IOBUF (...);
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input I, T;
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endmodule
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(* iopad_external_pin = "IO" *)
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module IOBUF_DCIEN (...);
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parameter integer DRIVE = 12;
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parameter IBUF_LOW_PWR = "TRUE";
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@ -2216,6 +2278,7 @@ module IOBUF_DCIEN (...);
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input T;
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endmodule
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(* iopad_external_pin = "IO" *)
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module IOBUF_INTERMDISABLE (...);
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parameter integer DRIVE = 12;
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parameter IBUF_LOW_PWR = "TRUE";
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@ -2231,6 +2294,7 @@ module IOBUF_INTERMDISABLE (...);
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input T;
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endmodule
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(* iopad_external_pin = "IO" *)
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module IOBUFDS (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2242,6 +2306,7 @@ module IOBUFDS (...);
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input I, T;
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endmodule
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(* iopad_external_pin = "IO,IOB" *)
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module IOBUFDS_DCIEN (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2259,6 +2324,7 @@ module IOBUFDS_DCIEN (...);
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input T;
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endmodule
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(* iopad_external_pin = "IO,IOB" *)
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module IOBUFDS_DIFF_OUT (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2273,6 +2339,7 @@ module IOBUFDS_DIFF_OUT (...);
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input TS;
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endmodule
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(* iopad_external_pin = "IO,IOB" *)
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module IOBUFDS_DIFF_OUT_DCIEN (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2291,6 +2358,7 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
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input TS;
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endmodule
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(* iopad_external_pin = "IO,IOB" *)
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module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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@ -2309,6 +2377,7 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
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input TS;
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endmodule
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(* clkbuf_sink = "CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB" *)
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module ISERDESE2 (...);
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parameter DATA_RATE = "DDR";
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parameter integer DATA_WIDTH = 4;
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@ -2529,6 +2598,7 @@ module MMCME2_BASE (...);
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input RST;
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endmodule
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(* iopad_external_pin = "O,OB" *)
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module OBUFDS (...);
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parameter CAPACITANCE = "DONT_CARE";
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parameter IOSTANDARD = "DEFAULT";
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@ -2537,6 +2607,7 @@ module OBUFDS (...);
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input I;
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endmodule
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(* iopad_external_pin = "O" *)
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module OBUFT (...);
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parameter CAPACITANCE = "DONT_CARE";
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parameter integer DRIVE = 12;
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@ -2546,6 +2617,7 @@ module OBUFT (...);
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input I, T;
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endmodule
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(* iopad_external_pin = "O,OB" *)
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module OBUFTDS (...);
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parameter CAPACITANCE = "DONT_CARE";
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parameter IOSTANDARD = "DEFAULT";
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@ -2554,6 +2626,7 @@ module OBUFTDS (...);
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input I, T;
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endmodule
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(* clkbuf_sink = "C" *)
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module ODDR (...);
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output Q;
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input C;
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@ -2572,6 +2645,7 @@ module ODDR (...);
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parameter XON = "TRUE";
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endmodule
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(* clkbuf_sink = "C" *)
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module ODELAYE2 (...);
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parameter CINVCTRL_SEL = "FALSE";
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parameter DELAY_SRC = "ODATAIN";
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@ -2598,6 +2672,7 @@ module ODELAYE2 (...);
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input REGRST;
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endmodule
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(* clkbuf_sink = "CLK,CLKDIV" *)
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module OSERDESE2 (...);
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parameter DATA_RATE_OQ = "DDR";
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parameter DATA_RATE_TQ = "DDR";
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@ -2653,6 +2728,7 @@ module OSERDESE2 (...);
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input TCE;
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endmodule
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(* clkbuf_sink = "RDCLK,WRCLK" *)
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module OUT_FIFO (...);
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parameter integer ALMOST_EMPTY_VALUE = 1;
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parameter integer ALMOST_FULL_VALUE = 1;
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@ -3655,6 +3731,7 @@ module PULLUP (...);
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output O;
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endmodule
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(* clkbuf_sink = "WCLK" *)
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module RAM128X1S (...);
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parameter [127:0] INIT = 128'h00000000000000000000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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@ -3662,6 +3739,7 @@ module RAM128X1S (...);
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input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
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endmodule
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(* clkbuf_sink = "WCLK" *)
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module RAM256X1S (...);
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parameter [255:0] INIT = 256'h0;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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@ -3672,6 +3750,7 @@ module RAM256X1S (...);
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input WE;
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endmodule
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(* clkbuf_sink = "WCLK" *)
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module RAM32M (...);
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parameter [63:0] INIT_A = 64'h0000000000000000;
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parameter [63:0] INIT_B = 64'h0000000000000000;
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@ -3694,6 +3773,7 @@ module RAM32M (...);
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input WE;
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endmodule
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(* clkbuf_sink = "WCLK" *)
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module RAM32X1S (...);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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@ -3701,6 +3781,7 @@ module RAM32X1S (...);
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input A0, A1, A2, A3, A4, D, WCLK, WE;
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endmodule
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(* clkbuf_sink = "WCLK" *)
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module RAM32X1S_1 (...);
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parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
@ -3708,6 +3789,7 @@ module RAM32X1S_1 (...);
|
|||
input A0, A1, A2, A3, A4, D, WCLK, WE;
|
||||
endmodule
|
||||
|
||||
(* clkbuf_sink = "WCLK" *)
|
||||
module RAM32X2S (...);
|
||||
parameter [31:0] INIT_00 = 32'h00000000;
|
||||
parameter [31:0] INIT_01 = 32'h00000000;
|
||||
|
|
@ -3716,6 +3798,7 @@ module RAM32X2S (...);
|
|||
input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
|
||||
endmodule
|
||||
|
||||
(* clkbuf_sink = "WCLK" *)
|
||||
module RAM64M (...);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
|
|
@ -3738,6 +3821,7 @@ module RAM64M (...);
|
|||
input WE;
|
||||
endmodule
|
||||
|
||||
(* clkbuf_sink = "WCLK" *)
|
||||
module RAM64X1S (...);
|
||||
parameter [63:0] INIT = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
@ -3745,6 +3829,7 @@ module RAM64X1S (...);
|
|||
input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
|
||||
endmodule
|
||||
|
||||
(* clkbuf_sink = "WCLK" *)
|
||||
module RAM64X1S_1 (...);
|
||||
parameter [63:0] INIT = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
@ -3752,6 +3837,7 @@ module RAM64X1S_1 (...);
|
|||
input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
|
||||
endmodule
|
||||
|
||||
(* clkbuf_sink = "WCLK" *)
|
||||
module RAM64X2S (...);
|
||||
parameter [63:0] INIT_00 = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_01 = 64'h0000000000000000;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue