mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
Code Activity

Add "whitebox" attribute, add "read_verilog -wb"

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-18 17:42:12 +02:00
parent ea8ac0aaad
commit f4abc21d8a
23 changed files with 81 additions and 42 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/spice/spice.cc
View file

@ -212,7 +212,7 @@ struct SpiceBackend : public Backend {
for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
if (module->get_blackbox_attribute())
continue;
if (module->processes.size() != 0)