3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 02:40:25 +00:00

Add "whitebox" attribute, add "read_verilog -wb"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-18 17:42:12 +02:00
parent ea8ac0aaad
commit f4abc21d8a
23 changed files with 81 additions and 42 deletions

View file

@ -739,7 +739,7 @@ struct SmvBackend : public Backend {
pool<Module*> modules;
for (auto module : design->modules())
if (!module->get_bool_attribute("\\blackbox") && !module->has_memories_warn() && !module->has_processes_warn())
if (!module->get_blackbox_attribute() && !module->has_memories_warn() && !module->has_processes_warn())
modules.insert(module);
if (template_f.is_open())