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Add "whitebox" attribute, add "read_verilog -wb"

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-18 17:42:12 +02:00
parent ea8ac0aaad
commit f4abc21d8a
23 changed files with 81 additions and 42 deletions
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2
backends/intersynth/intersynth.cc
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@ -127,7 +127,7 @@ struct IntersynthBackend : public Backend {
RTLIL::Module *module = module_it.second;
SigMap sigmap(module);
if (module->get_bool_attribute("\\blackbox"))
if (module->get_blackbox_attribute())
continue;
if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
continue;