mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Added $eq/$neq -> $logic_not/$reduce_bool optimization

Browse source
This commit is contained in:
Clifford Wolf 2015-04-29 07:28:15 +02:00
parent 9d067fecea
commit f483dce7c2
4 changed files with 38 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

15
kernel/rtlil.cc
View file

@ -3000,6 +3000,21 @@ bool RTLIL::SigSpec::is_fully_const() const
return true;
}
bool RTLIL::SigSpec::is_fully_zero() const
{
cover("kernel.rtlil.sigspec.is_fully_zero");
pack();
for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
if (it->width > 0 && it->wire != NULL)
return false;
for (size_t i = 0; i < it->data.size(); i++)
if (it->data[i] != RTLIL::State::S0)
return false;
}
return true;
}
bool RTLIL::SigSpec::is_fully_def() const
{
cover("kernel.rtlil.sigspec.is_fully_def");

1
kernel/rtlil.h
View file

@ -692,6 +692,7 @@ public:
bool is_chunk() const;
bool is_fully_const() const;
bool is_fully_zero() const;
bool is_fully_def() const;
bool is_fully_undef() const;
bool has_const() const;

4
passes/fsm/fsm_extract.cc
View file

@ -305,7 +305,9 @@ static void extract_fsm(RTLIL::Wire *wire)
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_b;
if (cell->hasPort("\\B"))
sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
if (cellport.second == "\\A" && !sig_b.is_fully_const())
continue;

19
passes/opt/opt_const.cc
View file

@ -548,6 +548,25 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
if ((cell->type == "$eq" || cell->type == "$ne") &&
(assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero()))
{
cover_list("opt.opt_const.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
log("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
log_id(module), "$eq" ? "$logic_not" : "$reduce_bool");
cell->type = cell->type == "$eq" ? "$logic_not" : "$reduce_bool";
if (assign_map(cell->getPort("\\A")).is_fully_zero()) {
cell->setPort("\\A", cell->getPort("\\B"));
cell->setParam("\\A_SIGNED", cell->getParam("\\B_SIGNED"));
cell->setParam("\\A_WIDTH", cell->getParam("\\B_WIDTH"));
}
cell->unsetPort("\\B");
cell->unsetParam("\\B_SIGNED");
cell->unsetParam("\\B_WIDTH");
did_something = true;
goto next_cell;
}
if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx") && assign_map(cell->getPort("\\B")).is_fully_const())
{
bool sign_ext = cell->type == "$sshr" && cell->getParam("\\A_SIGNED").as_bool();