mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-09 04:31:25 +00:00
Code Activity

Added $eq/$neq -> $logic_not/$reduce_bool optimization

Browse source
This commit is contained in:
Clifford Wolf 2015-04-29 07:28:15 +02:00
parent 9d067fecea
commit f483dce7c2
4 changed files with 38 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/fsm/fsm_extract.cc
View file

@ -305,7 +305,9 @@ static void extract_fsm(RTLIL::Wire *wire)
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_b;
if (cell->hasPort("\\B"))
sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
if (cellport.second == "\\A" && !sig_b.is_fully_const())
continue;