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Merge pull request #729 from whitequark/write_verilog_initial

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write_verilog: correctly map RTLIL `sync init`
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Clifford Wolf 2018-12-16 15:50:16 +01:00 committed by GitHub
parent 0c69f1d777 7fe770a441
commit f481ad4d44
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1 changed files with 2 additions and 0 deletions
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backends/verilog/verilog_backend.cc
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@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
if (sync->type == RTLIL::STa) {
f << stringf("%s" "always @* begin\n", indent.c_str());
} else if (sync->type == RTLIL::STi) {
f << stringf("%s" "initial begin\n", indent.c_str());
} else {
f << stringf("%s" "always @(", indent.c_str());
if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1)