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Working on extensions doc

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Moved the last files out of the resources directory.
Some tidy up/reformatting of the extensions to allow literalincludes from `my_cmd.cc`.
Most (all?) of the getting started guidelines file is either in the quick guide section, or sections referenced by it.  Instead of including it verbatim, we'll instead just leave a reference to it but then jump straight into the quick guide.
Include an image for the absval generated module.  Still needs more surrounding text but it's good enough for now.

Also includes some other minor tidying, including removing the no longer used abc_01 code example.
This commit is contained in:
Krystine Sherwin 2023-12-13 11:34:42 +13:00
parent afe8eff790
commit f44e8d0124
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12 changed files with 120 additions and 226 deletions
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1
docs/source/code_examples/synth_flow/Makefile
View file

@ -3,7 +3,6 @@ TARGETS += proc_01 proc_02 proc_03
TARGETS += opt_01 opt_02 opt_03 opt_04
TARGETS += memory_01 memory_02
TARGETS += techmap_01
TARGETS += abc_01
PROGRAM_PREFIX :=

10
docs/source/code_examples/synth_flow/abc_01.v
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@ -1,10 +0,0 @@
module test(input clk, a, b, c,
output reg y);
reg [2:0] q1, q2;
always @(posedge clk) begin
q1 <= { a, b, c };
q2 <= q1;
y <= ^q2;
end
endmodule

5
docs/source/code_examples/synth_flow/abc_01.ys
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@ -1,5 +0,0 @@
read_verilog abc_01.v
read_verilog -lib abc_01_cells.v
hierarchy -check -top test
proc; opt; techmap
abc -dff -liberty abc_01_cells.lib;;

54
docs/source/code_examples/synth_flow/abc_01_cells.lib
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@ -1,54 +0,0 @@
// test comment
/* test comment */
library(demo) {
cell(BUF) {
area: 6;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A"; }
}
cell(NOT) {
area: 3;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A'"; }
}
cell(NAND) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A*B)'"; }
}
cell(NOR) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A+B)'"; }
}
cell(DFF) {
area: 18;
ff(IQ, IQN) { clocked_on: C;
next_state: D; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
}
cell(DFFSR) {
area: 18;
ff(IQ, IQN) { clocked_on: C;
next_state: D;
preset: S;
clear: R; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(S) { direction: input; }
pin(R) { direction: input; }
}
}

40
docs/source/code_examples/synth_flow/abc_01_cells.v
View file

@ -1,40 +0,0 @@
module BUF(A, Y);
input A;
output Y = A;
endmodule
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
module DFF(C, D, Q);
input C, D;
output reg Q;
always @(posedge C)
Q <= D;
endmodule
module DFFSR(C, D, Q, S, R);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
endmodule