Working on extensions doc

Moved the last files out of the resources directory.
Some tidy up/reformatting of the extensions to allow literalincludes from `my_cmd.cc`.
Most (all?) of the getting started guidelines file is either in the quick guide section, or sections referenced by it.  Instead of including it verbatim, we'll instead just leave a reference to it but then jump straight into the quick guide.
Include an image for the absval generated module.  Still needs more surrounding text but it's good enough for now.

Also includes some other minor tidying, including removing the no longer used abc_01 code example.

docs/source/code_examples/extensions/.gitignore

@@ -0,0 +1,2 @@
+my_cmd.so
+my_cmd.d

docs/source/code_examples/extensions/Makefile

@@ -0,0 +1,29 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+all: test0.log test1.log test2.log
+
+dots: test1.dot
+
+CXXFLAGS=$(shell $(YOSYS)-config --cxxflags)
+DATDIR=$(shell $(YOSYS)-config --datdir)
+
+my_cmd.so: my_cmd.cc
+	$(YOSYS)-config --exec --cxx $(subst $(DATDIR),../../share,$(CXXFLAGS)) --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
+
+test0.log: my_cmd.so
+	$(YOSYS) -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
+	mv test0.log_new test0.log
+
+test1.log: my_cmd.so
+	$(YOSYS) -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
+	mv test1.log_new test1.log
+
+test1.dot:
+	$(YOSYS) -m ./my_cmd.so -p 'test1; show -format dot -prefix test1'
+
+test2.log: my_cmd.so
+	$(YOSYS) -Ql test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' sigmap_test.v
+	mv test2.log_new test2.log
+

docs/source/code_examples/extensions/absval_ref.v

@@ -0,0 +1,3 @@
+module absval_ref(input signed [3:0] a, output [3:0] y);
+	assign y = a[3] ? -a : a;
+endmodule

docs/source/code_examples/extensions/my_cmd.cc

@@ -0,0 +1,76 @@
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct MyPass : public Pass {
+    MyPass() : Pass("my_cmd", "just a simple test") { }
+    void execute(std::vector<std::string> args, RTLIL::Design *design) override
+    {
+        log("Arguments to my_cmd:\n");
+        for (auto &arg : args)
+            log("  %s\n", arg.c_str());
+
+        log("Modules in current design:\n");
+        for (auto mod : design->modules())
+            log("  %s (%d wires, %d cells)\n", log_id(mod),
+                    GetSize(mod->wires()), GetSize(mod->cells()));
+    }
+} MyPass;
+
+
+struct Test1Pass : public Pass {
+    Test1Pass() : Pass("test1", "creating the absval module") { }
+    void execute(std::vector<std::string>, RTLIL::Design *design) override
+    {
+        if (design->has("\\absval") != 0)
+            log_error("A module with the name absval already exists!\n");
+
+        RTLIL::Module *module = design->addModule("\\absval");
+        log("Name of this module: %s\n", log_id(module));
+
+        RTLIL::Wire *a = module->addWire("\\a", 4);
+        a->port_input = true;
+        a->port_id = 1;
+
+        RTLIL::Wire *y = module->addWire("\\y", 4);
+        y->port_output = true;
+        y->port_id = 2;
+
+        RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
+        module->addNeg(NEW_ID, a, a_inv, true);
+        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
+
+	module->fixup_ports();
+    }
+} Test1Pass;
+
+
+struct Test2Pass : public Pass {
+    Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
+    void execute(std::vector<std::string>, RTLIL::Design *design) override
+    {
+        if (design->selection_stack.back().empty())
+            log_cmd_error("This command can't operator on an empty selection!\n");
+
+        RTLIL::Module *module = design->modules_.at("\\test");
+
+        RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y"));
+        log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
+
+        SigMap sigmap(module);
+        log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
+                          sigmap(y) == sigmap(a)); // will print "1 1 1"
+
+        log("Mapped signal x: %s\n", log_signal(sigmap(x)));
+
+        log_header(design, "Doing important stuff!\n");
+        log_push();
+        for (int i = 0; i < 10; i++)
+            log("Log message #%d.\n", i);
+        log_pop();
+    }
+} Test2Pass;
+
+PRIVATE_NAMESPACE_END

docs/source/code_examples/extensions/sigmap_test.v

@@ -0,0 +1,3 @@
+module test(input a, output x, y);
+	assign x = a, y = a;
+endmodule

docs/source/code_examples/synth_flow/Makefile

@@ -3,7 +3,6 @@ TARGETS += proc_01 proc_02 proc_03
 TARGETS += opt_01 opt_02 opt_03 opt_04
 TARGETS += memory_01 memory_02
 TARGETS += techmap_01
-TARGETS += abc_01
 
 PROGRAM_PREFIX :=
 

docs/source/code_examples/synth_flow/abc_01.v

@@ -1,10 +0,0 @@
-module test(input clk, a, b, c,
-            output reg y);
-
-	reg [2:0] q1, q2;
-	always @(posedge clk) begin
-		q1 <= { a, b, c };
-		q2 <= q1;
-		y <= ^q2;
-	end
-endmodule

docs/source/code_examples/synth_flow/abc_01.ys

@@ -1,5 +0,0 @@
-read_verilog abc_01.v
-read_verilog -lib abc_01_cells.v
-hierarchy -check -top test
-proc; opt; techmap
-abc -dff -liberty abc_01_cells.lib;;

docs/source/code_examples/synth_flow/abc_01_cells.lib

@@ -1,54 +0,0 @@
-// test comment
-/* test comment */
-library(demo) {
-  cell(BUF) {
-    area: 6;
-    pin(A) { direction: input; }
-    pin(Y) { direction: output;
-              function: "A"; }
-  }
-  cell(NOT) {
-    area: 3;
-    pin(A) { direction: input; }
-    pin(Y) { direction: output;
-              function: "A'"; }
-  }
-  cell(NAND) {
-    area: 4;
-    pin(A) { direction: input; }
-    pin(B) { direction: input; }
-    pin(Y) { direction: output;
-             function: "(A*B)'"; }
-  }
-  cell(NOR) {
-    area: 4;
-    pin(A) { direction: input; }
-    pin(B) { direction: input; }
-    pin(Y) { direction: output;
-             function: "(A+B)'"; }
-  }
-  cell(DFF) {
-    area: 18;
-    ff(IQ, IQN) { clocked_on: C;
-                  next_state: D; }
-    pin(C) { direction: input;
-                 clock: true; }
-    pin(D) { direction: input; }
-    pin(Q) { direction: output;
-              function: "IQ"; }
-  }
-  cell(DFFSR) {
-    area: 18;
-    ff(IQ, IQN) { clocked_on: C;
-                  next_state: D;
-                      preset: S;
-                       clear: R; }
-    pin(C) { direction: input;
-                 clock: true; }
-    pin(D) { direction: input; }
-    pin(Q) { direction: output;
-              function: "IQ"; }
-    pin(S) { direction: input; }
-    pin(R) { direction: input; }
-  }
-}

docs/source/code_examples/synth_flow/abc_01_cells.v

@@ -1,40 +0,0 @@
-
-module BUF(A, Y);
-input A;
-output Y = A;
-endmodule
-
-module NOT(A, Y);
-input A;
-output Y = ~A;
-endmodule
-
-module NAND(A, B, Y);
-input A, B;
-output Y = ~(A & B);
-endmodule
-
-module NOR(A, B, Y);
-input A, B;
-output Y = ~(A | B);
-endmodule
-
-module DFF(C, D, Q);
-input C, D;
-output reg Q;
-always @(posedge C)
-	Q <= D;
-endmodule
-
-module DFFSR(C, D, Q, S, R);
-input C, D, S, R;
-output reg Q;
-always @(posedge C, posedge S, posedge R)
-	if (S)
-		Q <= 1'b1;
-	else if (R)
-		Q <= 1'b0;
-	else
-		Q <= D;
-endmodule
-