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https://github.com/YosysHQ/yosys
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Properly clean up unused "init" attributes
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parent
a7ab9172f9
commit
f43815054e
2 changed files with 36 additions and 6 deletions
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@ -63,16 +63,26 @@ struct DffinitPass : public Pass {
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SigMap sigmap(module);
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dict<SigBit, State> init_bits;
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pool<SigBit> cleanup_bits;
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pool<SigBit> used_bits;
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for (auto wire : module->selected_wires())
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for (auto wire : module->selected_wires()) {
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if (wire->attributes.count("\\init")) {
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Const value = wire->attributes.at("\\init");
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for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
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init_bits[sigmap(SigBit(wire, i))] = value[i];
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}
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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used_bits.insert(bit);
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}
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for (auto cell : module->selected_cells())
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{
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for (auto it : cell->connections())
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if (!cell->known() || cell->input(it.first))
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for (auto bit : sigmap(it.second))
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used_bits.insert(bit);
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if (ff_types.count(cell->type) == 0)
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continue;
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@ -104,11 +114,15 @@ struct DffinitPass : public Pass {
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for (auto wire : module->selected_wires())
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if (wire->attributes.count("\\init")) {
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Const value = wire->attributes.at("\\init");
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Const &value = wire->attributes.at("\\init");
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bool do_cleanup = true;
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for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++)
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if (cleanup_bits.count(sigmap(SigBit(wire, i))) == 0)
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for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) {
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SigBit bit = sigmap(SigBit(wire, i));
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if (cleanup_bits.count(bit) || !used_bits.count(bit))
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value[i] = State::Sx;
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else if (value[i] != State::Sx)
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do_cleanup = false;
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}
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if (do_cleanup) {
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log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
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wire->attributes.erase("\\init");
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