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quicklogic: PolarPro 3 support

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Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
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Lofty 2021-03-17 02:34:30 +00:00 • committed by Marcelina Kościelnicka
parent 8740fdf1d7
commit f4298b057a
20 changed files with 1033 additions and 0 deletions
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tests/arch/quicklogic/dffs.ys Normal file
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read_verilog ../common/dffs.v
rename dff my_dff # Work around conflicting module names between test and vendor cells
rename dffe my_dffe
design -save read
hierarchy -top my_dff
proc
equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-none t:*
design -load read
hierarchy -top my_dffe
proc
equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-none t:*