mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-09 20:50:51 +00:00
Code Activity

Added examples/ top-level directory

Browse source
This commit is contained in:
Clifford Wolf 2015-10-13 15:40:21 +02:00
parent f13e387321
commit f42218682d
17 changed files with 7 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

44
techlibs/cmos/cmos_cells.v
View file

@ -1,44 +0,0 @@
module BUF(A, Y);
input A;
output Y;
assign Y = A;
endmodule
module NOT(A, Y);
input A;
output Y;
assign Y = ~A;
endmodule
module NAND(A, B, Y);
input A, B;
output Y;
assign Y = ~(A & B);
endmodule
module NOR(A, B, Y);
input A, B;
output Y;
assign Y = ~(A | B);
endmodule
module DFF(C, D, Q);
input C, D;
output reg Q;
always @(posedge C)
Q <= D;
endmodule
module DFFSR(C, D, Q, S, R);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
endmodule