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Added examples/ top-level directory

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This commit is contained in:
Clifford Wolf 2015-10-13 15:40:21 +02:00
parent f13e387321
commit f42218682d
17 changed files with 7 additions and 4 deletions
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examples/cmos/counter.ys Normal file
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read_verilog counter.v
read_verilog -lib cmos_cells.v
proc;; memory;; techmap;;
dfflibmap -liberty cmos_cells.lib
abc -liberty cmos_cells.lib;;
# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
# dfflibmap -liberty osu025_stdcells.lib
# abc -liberty osu025_stdcells.lib;;
write_verilog synth.v
write_spice synth.sp