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Added examples/ top-level directory

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Clifford Wolf 2015-10-13 15:40:21 +02:00
parent f13e387321
commit f42218682d
17 changed files with 7 additions and 4 deletions
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examples/basys3/example.v Normal file
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module example(CLK, LD);
input CLK;
output [15:0] LD;
wire clock;
reg [15:0] leds;
BUFG CLK_BUF (.I(CLK), .O(clock));
OBUF LD_BUF[15:0] (.I(leds), .O(LD));
parameter COUNTBITS = 26;
reg [COUNTBITS-1:0] counter;
always @(posedge CLK) begin
counter <= counter + 1;
if (counter[COUNTBITS-1])
leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
else
leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
end
endmodule