From f3c87610f51a20feecac94a37535f374fcfcbdca Mon Sep 17 00:00:00 2001 From: nataliakokoromyti Date: Sat, 24 Jan 2026 23:46:45 -0800 Subject: [PATCH] verific: allow mixed SV/VHDL in -f files --- frontends/verific/verific.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 92df86fd5..67e70d5e7 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3744,10 +3744,28 @@ struct VerificPass : public Pass { veri_file::DefineMacro("VERIFIC"); veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS"); +#ifdef VERIFIC_VHDL_SUPPORT + int i; + FOREACH_ARRAY_ITEM(file_names, i, filename) { + std::string filename_str = filename; + if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") || + (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) { + vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); + if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_file::VHDL_2019)) { + verific_error_msg.clear(); + log_cmd_error("Reading VHDL sources failed.\n"); + } + } else if (!veri_file::Analyze(filename, analysis_mode, work.c_str())) { + verific_error_msg.clear(); + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } + } +#else if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } +#endif delete file_names; verific_import_pending = true;