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Added help messages to memory_* passes

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This commit is contained in:
Clifford Wolf 2013-03-01 10:17:35 +01:00
parent f952309c81
commit f3a849512f
4 changed files with 71 additions and 15 deletions
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19
passes/memory/memory_map.cc
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@ -312,23 +312,34 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
return;
}
static void handle_module(RTLIL::Module *module)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::Cell*> cells;
for (auto &it : module->cells)
if (it.second->type == "$mem")
if (it.second->type == "$mem" && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : cells)
handle_cell(module, cell);
}
struct MemoryMapPass : public Pass {
MemoryMapPass() : Pass("memory_map") { }
MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" memory_map [selection]\n");
log("\n");
log("This pass converts multiport memory cells as generated by the memory_collect\n");
log("pass to word-wide DFFs and address decoders.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
handle_module(mod_it.second);
if (design->selected(mod_it.second))
handle_module(design, mod_it.second);
}
} MemoryMapPass;