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Added help messages to memory_* passes
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parent
f952309c81
commit
f3a849512f
4 changed files with 71 additions and 15 deletions
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@ -178,9 +178,11 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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#endif
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static void handle_module(RTLIL::Module *module)
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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for (auto &cell_it : module->cells) {
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if (!design->selected(module, cell_it.second))
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continue;
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if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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handle_wr_cell(module, cell_it.second);
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if (cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
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@ -189,12 +191,24 @@ static void handle_module(RTLIL::Module *module)
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}
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struct MemoryDffPass : public Pass {
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MemoryDffPass() : Pass("memory_dff") { }
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MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_dff [selection]\n");
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log("\n");
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log("This pass detects DFFs at memory ports and merges them into the memory port.\n");
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log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
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log("interface and yields a synchronous memory port.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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handle_module(mod_it.second);
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second);
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}
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} MemoryDffPass;
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