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Added help messages to memory_* passes
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parent
f952309c81
commit
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4 changed files with 71 additions and 15 deletions
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@ -161,22 +161,38 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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module->cells[mem->name] = mem;
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}
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static void handle_module(RTLIL::Module *module)
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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for (auto &mem_it : module->memories) {
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handle_memory(module, mem_it.second);
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delete mem_it.second;
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std::vector<RTLIL::IdString> delme;
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for (auto &mem_it : module->memories)
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if (design->selected(module, mem_it.second)) {
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handle_memory(module, mem_it.second);
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delme.push_back(mem_it.first);
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}
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for (auto &it : delme) {
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delete module->memories.at(it);
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module->memories.erase(it);
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}
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module->memories.clear();
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}
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struct MemoryCollectPass : public Pass {
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MemoryCollectPass() : Pass("memory_collect") { }
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MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_collect [selection]\n");
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log("\n");
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log("This pass collects memories and memory ports and creates generic multiport\n");
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log("memory cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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handle_module(mod_it.second);
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second);
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}
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} MemoryCollectPass;
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