mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 04:28:18 +00:00
Fixes and error check
This commit is contained in:
parent
ede348cdc2
commit
f37ac5d934
|
@ -1095,6 +1095,8 @@ struct SimWorker : SimShared
|
||||||
void run_cosim_aiger_witness(Module *topmod)
|
void run_cosim_aiger_witness(Module *topmod)
|
||||||
{
|
{
|
||||||
log_assert(top == nullptr);
|
log_assert(top == nullptr);
|
||||||
|
if ((clock.size()+clockn.size())==0)
|
||||||
|
log_error("Clock signal must be specified.\n");
|
||||||
std::ifstream mf(map_filename);
|
std::ifstream mf(map_filename);
|
||||||
std::string type, symbol;
|
std::string type, symbol;
|
||||||
int variable, index;
|
int variable, index;
|
||||||
|
@ -1213,6 +1215,8 @@ struct SimWorker : SimShared
|
||||||
void run_cosim_btor2_witness(Module *topmod)
|
void run_cosim_btor2_witness(Module *topmod)
|
||||||
{
|
{
|
||||||
log_assert(top == nullptr);
|
log_assert(top == nullptr);
|
||||||
|
if ((clock.size()+clockn.size())==0)
|
||||||
|
log_error("Clock signal must be specified.\n");
|
||||||
std::ifstream f;
|
std::ifstream f;
|
||||||
f.open(sim_filename.c_str());
|
f.open(sim_filename.c_str());
|
||||||
if (f.fail() || GetSize(sim_filename) == 0)
|
if (f.fail() || GetSize(sim_filename) == 0)
|
||||||
|
@ -1278,7 +1282,7 @@ struct SimWorker : SimShared
|
||||||
if ((int)parts[1].size() != w->width)
|
if ((int)parts[1].size() != w->width)
|
||||||
log_error("Size of wire %s is different than provided data.\n", log_signal(w));
|
log_error("Size of wire %s is different than provided data.\n", log_signal(w));
|
||||||
|
|
||||||
top->set_state(w, Const(parts[1]));
|
top->set_state(w, Const::from_string(parts[1]));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue