mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Update Xilinx cell definitions, fixes #3699

Browse source
This commit is contained in:
Miodrag Milanovic 2023-03-21 08:53:22 +01:00 • committed by myrtle
parent 23826e5152
commit f35bdaa527
3 changed files with 16 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/xilinx/cells_xtra.py
View file

@ -706,7 +706,7 @@ def xtract_cell_decl(cell, dirs, outf):
if __name__ == '__main__':
parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.')
parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2022.2')
parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7')
args = parser.parse_args()