mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
xilinx: Use dfflegalize.
This commit is contained in:
Marcelina Kościelnicka
parent
7ed9d18907
commit
f313211c32
6 changed files with 131 additions and 484 deletions
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@ -42,8 +42,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut4_lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut6_lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut6_lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
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@ -18,43 +18,6 @@
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*
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*
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*/
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*/
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// Convert negative-polarity reset to positive-polarity
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(* techmap_celltype = "$_DFF_NN0_" *)
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module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_DFF_PN0_" *)
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module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_DFF_NN1_" *)
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module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_DFF_PN1_" *)
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module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_DFFE_NN0P_" *)
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module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$_DFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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(* techmap_celltype = "$_DFFE_PN0P_" *)
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module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$_DFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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(* techmap_celltype = "$_DFFE_NN1P_" *)
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module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$_DFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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(* techmap_celltype = "$_DFFE_PN1P_" *)
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module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$_DFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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(* techmap_celltype = "$_SDFF_NN0_" *)
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module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$_SDFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_SDFF_PN0_" *)
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module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$_SDFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_SDFF_NN1_" *)
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module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$_SDFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_SDFF_PN1_" *)
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module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$_SDFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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(* techmap_celltype = "$_SDFFE_NN0P_" *)
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module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$_SDFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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(* techmap_celltype = "$_SDFFE_PN0P_" *)
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module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$_SDFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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(* techmap_celltype = "$_SDFFE_NN1P_" *)
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module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$_SDFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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(* techmap_celltype = "$_SDFFE_PN1P_" *)
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module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$_SDFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
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module \$__SHREG_ (input C, input D, input E, output Q);
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module \$__SHREG_ (input C, input D, input E, output Q);
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parameter DEPTH = 0;
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parameter DEPTH = 0;
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parameter [DEPTH-1:0] INIT = 0;
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parameter [DEPTH-1:0] INIT = 0;
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120
techlibs/xilinx/ff_map.v
Normal file
120
techlibs/xilinx/ff_map.v
Normal file
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@ -0,0 +1,120 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`ifndef _NO_FFS
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// Async reset, enable.
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module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Async set and reset, enable.
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module \$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Sync reset, enable.
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module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Latches with reset.
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module \$_DLATCH_NP0_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_PP0_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_NP1_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_PP1_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Latches with set and reset.
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module \$_DLATCH_NPP_ (input E, S, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_PPP_ (input E, S, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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`endif
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@ -342,13 +342,6 @@ struct SynthXilinxPass : public ScriptPass
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std::string lut_size_s = std::to_string(lut_size);
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std::string lut_size_s = std::to_string(lut_size);
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if (help_mode)
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if (help_mode)
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lut_size_s = "[46]";
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lut_size_s = "[46]";
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std::string ff_map_file;
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if (help_mode)
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ff_map_file = "+/xilinx/{family}_ff_map.v";
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else if (family == "xc6s")
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ff_map_file = "+/xilinx/xc6s_ff_map.v";
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else
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ff_map_file = "+/xilinx/xc7_ff_map.v";
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if (check_label("begin")) {
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if (check_label("begin")) {
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std::string read_args;
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std::string read_args;
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@ -595,11 +588,17 @@ struct SynthXilinxPass : public ScriptPass
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run("clean");
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run("clean");
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}
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}
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if (check_label("map_ffs", "('-abc9' only)")) {
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if (check_label("map_ffs")) {
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if (family == "xc6s")
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run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r -cell $_DLATCH_?P?_ r", "(for xc6s)");
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else if (family == "xc6v" || family == "xc7" || family == "xcu" || family == "xcup")
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run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01", "(for xc6v, xc7, xcu, xcup)");
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else
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run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_DFFSRE_?PPP_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01 -cell $_DLATCHSR_?PP_ 01", "(for xc5v and older)");
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if (abc9 || help_mode) {
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if (abc9 || help_mode) {
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if (dff || help_mode)
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if (dff || help_mode)
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run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "('-dff' only)");
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run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)");
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run("techmap -map " + ff_map_file);
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run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)");
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}
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}
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}
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}
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@ -659,7 +658,7 @@ struct SynthXilinxPass : public ScriptPass
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run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
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run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
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std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
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std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
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if (help_mode || !abc9)
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if (help_mode || !abc9)
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techmap_args += stringf(" -map %s", ff_map_file.c_str());
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techmap_args += stringf(" -map +/xilinx/ff_map.v");
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techmap_args += " -D LUT_WIDTH=" + lut_size_s;
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techmap_args += " -D LUT_WIDTH=" + lut_size_s;
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run("techmap " + techmap_args);
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run("techmap " + techmap_args);
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if (help_mode)
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if (help_mode)
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@ -1,256 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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|
||||||
* purpose with or without fee is hereby granted, provided that the above
|
|
||||||
* copyright notice and this permission notice appear in all copies.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
||||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
||||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
||||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
||||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
||||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
// ============================================================================
|
|
||||||
// FF mapping for Spartan 6. The primitives used are the same as Series 7,
|
|
||||||
// but with one major difference: the initial value is implied by the
|
|
||||||
// primitive type used (FFs with reset pin must have INIT set to 0 or x, FFs
|
|
||||||
// with set pin must have INIT set to 1 or x). For Yosys primitives without
|
|
||||||
// set/reset, this means we have to pick the primitive type based on the INIT
|
|
||||||
// value.
|
|
||||||
|
|
||||||
`ifndef _NO_FFS
|
|
||||||
|
|
||||||
// No reset.
|
|
||||||
|
|
||||||
module \$_DFF_N_ (input D, C, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
|
|
||||||
else
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFF_P_ (input D, C, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
|
|
||||||
else
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// No reset, enable.
|
|
||||||
|
|
||||||
module \$_DFFE_NP_ (input D, C, E, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0));
|
|
||||||
else
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFFE_PP_ (input D, C, E, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0));
|
|
||||||
else
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Async reset.
|
|
||||||
|
|
||||||
module \$_DFF_NP0_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFF_PP0_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFF_NP1_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
|
||||||
else
|
|
||||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFF_PP1_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
|
||||||
else
|
|
||||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Async reset, enable.
|
|
||||||
|
|
||||||
module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
|
||||||
else
|
|
||||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
|
||||||
else
|
|
||||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Sync reset.
|
|
||||||
|
|
||||||
module \$_SDFF_NP0_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFF_PP0_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_SDFF_NP1_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with set initialized to 0");
|
|
||||||
else
|
|
||||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFF_PP1_ (input D, C, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with set initialized to 0");
|
|
||||||
else
|
|
||||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Sync reset, enable.
|
|
||||||
|
|
||||||
module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
|
|
||||||
else
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with set initialized to 0");
|
|
||||||
else
|
|
||||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
|
||||||
$error("Spartan 6 doesn't support FFs with set initialized to 0");
|
|
||||||
else
|
|
||||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Latches (no reset).
|
|
||||||
|
|
||||||
module \$_DLATCH_N_ (input E, D, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0));
|
|
||||||
else
|
|
||||||
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DLATCH_P_ (input E, D, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0));
|
|
||||||
else
|
|
||||||
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Latches with reset (TODO).
|
|
||||||
|
|
||||||
`endif
|
|
||||||
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
* yosys -- Yosys Open SYnthesis Suite
|
|
||||||
*
|
|
||||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
|
||||||
*
|
|
||||||
* Permission to use, copy, modify, and/or distribute this software for any
|
|
||||||
* purpose with or without fee is hereby granted, provided that the above
|
|
||||||
* copyright notice and this permission notice appear in all copies.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
||||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
||||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
||||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
||||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
||||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
// ============================================================================
|
|
||||||
// FF mapping for Virtex 6, Series 7 and Ultrascale. These families support
|
|
||||||
// the following features:
|
|
||||||
//
|
|
||||||
// - a CLB flip-flop can be used as a latch or as a flip-flop
|
|
||||||
// - a CLB flip-flop has the following pins:
|
|
||||||
//
|
|
||||||
// - data input
|
|
||||||
// - clock (or gate for latches) (with optional inversion)
|
|
||||||
// - clock enable (or gate enable, which is just ANDed with gate — unused by
|
|
||||||
// synthesis)
|
|
||||||
// - either a set or a reset input, which (for FFs) can be either
|
|
||||||
// synchronous or asynchronous (with optional inversion)
|
|
||||||
// - data output
|
|
||||||
//
|
|
||||||
// - a flip-flop also has an initial value, which is set at device
|
|
||||||
// initialization (or whenever GSR is asserted)
|
|
||||||
|
|
||||||
`ifndef _NO_FFS
|
|
||||||
|
|
||||||
// No reset.
|
|
||||||
|
|
||||||
module \$_DFF_N_ (input D, C, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFF_P_ (input D, C, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// No reset, enable.
|
|
||||||
|
|
||||||
module \$_DFFE_NP_ (input D, C, E, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFFE_PP_ (input D, C, E, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Async reset.
|
|
||||||
|
|
||||||
module \$_DFF_NP0_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFF_PP0_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFF_NP1_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFF_PP1_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Async reset, enable.
|
|
||||||
|
|
||||||
module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Sync reset.
|
|
||||||
|
|
||||||
module \$_SDFF_NP0_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFF_PP0_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_SDFF_NP1_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFF_PP1_ (input D, C, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Sync reset, enable.
|
|
||||||
|
|
||||||
module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Latches (no reset).
|
|
||||||
|
|
||||||
module \$_DLATCH_N_ (input E, D, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
module \$_DLATCH_P_ (input E, D, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// Latches with reset (TODO).
|
|
||||||
|
|
||||||
`endif
|
|
||||||
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue