From f2b1bcf6e6b7dd3d09837cc877dd80d1351bde5d Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 14 Oct 2025 14:12:24 +1300
Subject: [PATCH] Add tests/verilog/local_include.*

`read_verilog` supports checking both the current directory and the source directory for relative includes.  Make sure we aren't regressing that.
---
 tests/verilog/.gitignore       |  2 ++
 tests/verilog/local_include.sh | 30 ++++++++++++++++++++++++++++++
 tests/verilog/local_include.v  |  4 ++++
 3 files changed, 36 insertions(+)
 create mode 100755 tests/verilog/local_include.sh
 create mode 100644 tests/verilog/local_include.v

diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
index 3702f10cf..d3e8690d5 100644
--- a/tests/verilog/.gitignore
+++ b/tests/verilog/.gitignore
@@ -4,3 +4,5 @@
 /roundtrip_proc_1.v
 /roundtrip_proc_2.v
 /assign_to_reg.v
+/subdir
+/temp_foo.v
diff --git a/tests/verilog/local_include.sh b/tests/verilog/local_include.sh
new file mode 100755
index 000000000..c10c7411b
--- /dev/null
+++ b/tests/verilog/local_include.sh
@@ -0,0 +1,30 @@
+#!/usr/bin/env bash
+
+set -eu
+
+# only works with read_verilog
+yosys='../../yosys -f verilog'
+test='-p hierarchy'
+subdir=subdir
+source=local_include.v
+include=temp_foo.v
+
+# no include file should fail
+rm -f $include
+echo "logger -expect error $include 1; read_verilog $source" | $yosys
+
+# both files local
+echo 'module foo (input a, output b); assign b = a; endmodule' > $include
+$yosys $test $source
+
+# include local to cwd
+mkdir -p $subdir
+cp -t $subdir $source
+$yosys $test $subdir/$source
+
+# include local to source
+mv -t $subdir $include
+$yosys $test $subdir/$source
+
+# include local to source, and source is given as an absolute path
+$yosys $test $(pwd)/$subdir/$source
diff --git a/tests/verilog/local_include.v b/tests/verilog/local_include.v
new file mode 100644
index 000000000..a677e888e
--- /dev/null
+++ b/tests/verilog/local_include.v
@@ -0,0 +1,4 @@
+`include "temp_foo.v"
+module top (input x, output y);
+	foo bar (.a(x), .b(y));
+endmodule