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xilinx: Add some missing blackbox cells.

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This commit is contained in:
Marcelina Kościelnicka 2020-12-19 18:14:06 +01:00
parent 5ffb676fa9
commit f2932628fc
3 changed files with 6838 additions and 1360 deletions
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99
techlibs/xilinx/cells_sim.v
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@ -2023,6 +2023,105 @@ module RAM64M8 (
end
endmodule
module RAM32X16DR8 (
output DOA,
output DOB,
output DOC,
output DOD,
output DOE,
output DOF,
output DOG,
output [1:0] DOH,
input [5:0] ADDRA, ADDRB, ADDRC, ADDRD, ADDRE, ADDRF, ADDRG,
input [4:0] ADDRH,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input [1:0] DIE,
input [1:0] DIF,
input [1:0] DIG,
input [1:0] DIH,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h;
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD];
assign DOE = mem_e[ADDRE];
assign DOF = mem_f[ADDRF];
assign DOG = mem_g[ADDRG];
assign DOH = mem_h[2*ADDRH+:2];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk)
if (WE) begin
mem_a[2*ADDRH+:2] <= DIA;
mem_b[2*ADDRH+:2] <= DIB;
mem_c[2*ADDRH+:2] <= DIC;
mem_d[2*ADDRH+:2] <= DID;
mem_e[2*ADDRH+:2] <= DIE;
mem_f[2*ADDRH+:2] <= DIF;
mem_g[2*ADDRH+:2] <= DIG;
mem_h[2*ADDRH+:2] <= DIH;
end
endmodule
module RAM64X8SW (
output [7:0] O,
input [5:0] A,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input [2:0] WSEL
);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
parameter [63:0] INIT_C = 64'h0000000000000000;
parameter [63:0] INIT_D = 64'h0000000000000000;
parameter [63:0] INIT_E = 64'h0000000000000000;
parameter [63:0] INIT_F = 64'h0000000000000000;
parameter [63:0] INIT_G = 64'h0000000000000000;
parameter [63:0] INIT_H = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [63:0] mem_a = INIT_A;
reg [63:0] mem_b = INIT_B;
reg [63:0] mem_c = INIT_C;
reg [63:0] mem_d = INIT_D;
reg [63:0] mem_e = INIT_E;
reg [63:0] mem_f = INIT_F;
reg [63:0] mem_g = INIT_G;
reg [63:0] mem_h = INIT_H;
assign O[7] = mem_a[A];
assign O[6] = mem_b[A];
assign O[5] = mem_c[A];
assign O[4] = mem_d[A];
assign O[3] = mem_e[A];
assign O[2] = mem_f[A];
assign O[1] = mem_g[A];
assign O[0] = mem_h[A];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk)
if (WE) begin
case (WSEL)
3'b111: mem_a[A] <= D;
3'b110: mem_b[A] <= D;
3'b101: mem_c[A] <= D;
3'b100: mem_d[A] <= D;
3'b011: mem_e[A] <= D;
3'b010: mem_f[A] <= D;
3'b001: mem_g[A] <= D;
3'b000: mem_h[A] <= D;
endcase
end
endmodule
// ROM.
module ROM16X1 (