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Implemented basic functionality of "extract" pass

This commit is contained in:
Clifford Wolf 2013-02-27 16:27:20 +01:00
parent c59d77aa30
commit f28b6aff40
3 changed files with 87 additions and 15 deletions

View file

@ -141,6 +141,16 @@ static void rmunused_module_signals(RTLIL::Module *module)
used_signals_nodrivers.add(it2.second);
}
}
for (auto &it : module->wires) {
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
assign_map.apply(sig);
used_signals.add(sig);
if (!wire->port_input)
used_signals_nodrivers.add(sig);
}
}
std::vector<RTLIL::Wire*> del_wires;
for (auto &it : module->wires) {