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Merge https://github.com/cliffordwolf/yosys

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This commit is contained in:
Andrew Zonenberg 2016-04-01 00:03:00 -07:00
commit f277267916
21 changed files with 439 additions and 366 deletions
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4
techlibs/common/prep.cc
View file

@ -69,7 +69,7 @@ struct PrepPass : public Pass {
log("\n");
log(" prep:\n");
log(" proc\n");
log(" opt_const\n");
log(" opt_expr -keepdc\n");
log(" opt_clean\n");
log(" check\n");
log(" opt -keepdc\n");
@ -134,7 +134,7 @@ struct PrepPass : public Pass {
if (check_label(active, run_from, run_to, "coarse"))
{
Pass::call(design, "proc");
Pass::call(design, "opt_const");
Pass::call(design, "opt_expr -keepdc");
Pass::call(design, "opt_clean");
Pass::call(design, "check");
Pass::call(design, "opt -keepdc");

153
techlibs/common/synth.cc
View file

@ -25,22 +25,11 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
struct SynthPass : public ScriptPass
{
if (!run_from.empty() && run_from == run_to) {
active = (label == run_from);
} else {
if (label == run_from)
active = true;
if (label == run_to)
active = false;
}
return active;
}
SynthPass() : ScriptPass("synth", "generic synthesis script") { }
struct SynthPass : public Pass {
SynthPass() : Pass("synth", "generic synthesis script") { }
virtual void help()
virtual void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -75,49 +64,28 @@ struct SynthPass : public Pass {
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
log("\n");
log(" begin:\n");
log(" hierarchy -check [-top <top>]\n");
log("\n");
log(" coarse:\n");
log(" proc\n");
log(" opt_const\n");
log(" opt_clean\n");
log(" check\n");
log(" opt\n");
log(" wreduce\n");
log(" alumacc\n");
log(" share\n");
log(" opt\n");
log(" fsm\n");
log(" opt -fast\n");
log(" memory -nomap\n");
log(" opt_clean\n");
log("\n");
log(" fine:\n");
log(" opt -fast -full\n");
log(" memory_map\n");
log(" opt -full\n");
log(" techmap\n");
log(" opt -fast\n");
#ifdef YOSYS_ENABLE_ABC
log(" abc -fast\n");
log(" opt -fast\n");
#endif
log("\n");
log(" check:\n");
log(" hierarchy -check\n");
log(" stat\n");
log(" check\n");
help_script();
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
std::string top_module, fsm_opts, memory_opts;
bool noalumacc, nofsm, noabc;
virtual void clear_flags() YS_OVERRIDE
{
std::string top_module, fsm_opts, memory_opts;
std::string run_from, run_to;
bool noalumacc = false;
bool nofsm = false;
bool noabc = false;
top_module.clear();
fsm_opts.clear();
memory_opts.clear();
noalumacc = false;
nofsm = false;
noabc = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -164,62 +132,69 @@ struct SynthPass : public Pass {
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
bool active = run_from.empty();
log_header("Executing SYNTH pass.\n");
log_push();
if (check_label(active, run_from, run_to, "begin"))
run_script(design, run_from, run_to);
log_pop();
}
virtual void script() YS_OVERRIDE
{
if (check_label("begin"))
{
if (top_module.empty())
Pass::call(design, stringf("hierarchy -check"));
else
Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
if (help_mode) {
run("hierarchy -check [-top <top>]");
} else {
if (top_module.empty())
run(stringf("hierarchy -check"));
else
run(stringf("hierarchy -check -top %s", top_module.c_str()));
}
}
if (check_label(active, run_from, run_to, "coarse"))
if (check_label("coarse"))
{
Pass::call(design, "proc");
Pass::call(design, "opt_const");
Pass::call(design, "opt_clean");
Pass::call(design, "check");
Pass::call(design, "opt");
Pass::call(design, "wreduce");
run("proc");
run("opt_expr");
run("opt_clean");
run("check");
run("opt");
run("wreduce");
if (!noalumacc)
Pass::call(design, "alumacc");
Pass::call(design, "share");
Pass::call(design, "opt");
run("alumacc");
run("share");
run("opt");
if (!nofsm)
Pass::call(design, "fsm" + fsm_opts);
Pass::call(design, "opt -fast");
Pass::call(design, "memory -nomap" + memory_opts);
Pass::call(design, "opt_clean");
run("fsm" + fsm_opts);
run("opt -fast");
run("memory -nomap" + memory_opts);
run("opt_clean");
}
if (check_label(active, run_from, run_to, "fine"))
if (check_label("fine"))
{
Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
Pass::call(design, "opt -full");
Pass::call(design, "techmap");
Pass::call(design, "opt -fast");
run("opt -fast -full");
run("memory_map");
run("opt -full");
run("techmap");
run("opt -fast");
if (!noabc) {
#ifdef YOSYS_ENABLE_ABC
Pass::call(design, "abc -fast");
Pass::call(design, "opt -fast");
run("abc -fast");
run("opt -fast");
#endif
}
}
if (check_label(active, run_from, run_to, "check"))
if (check_label("check"))
{
Pass::call(design, "hierarchy -check");
Pass::call(design, "stat");
Pass::call(design, "check");
run("hierarchy -check");
run("stat");
run("check");
}
log_pop();
}
} SynthPass;

4
techlibs/common/techmap.v
View file

@ -93,7 +93,7 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
integer i;
reg [WIDTH-1:0] buffer;
@ -136,7 +136,7 @@ module _90_shift_shiftx (A, B, Y);
localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
integer i;
reg [WIDTH-1:0] buffer;

12
techlibs/ice40/ice40_opt.cc
View file

@ -127,8 +127,8 @@ struct Ice40OptPass : public Pass {
log("\n");
log(" do\n");
log(" <ice40 specific optimizations>\n");
log(" opt_const -mux_undef -undriven [-full]\n");
log(" opt_share\n");
log(" opt_expr -mux_undef -undriven [-full]\n");
log(" opt_merge\n");
log(" opt_rmdff\n");
log(" opt_clean\n");
log(" while <changed design>\n");
@ -136,14 +136,14 @@ struct Ice40OptPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
string opt_const_args = "-mux_undef -undriven";
string opt_expr_args = "-mux_undef -undriven";
log_header("Executing ICE40_OPT pass (performing simple optimizations).\n");
log_push();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-full") {
opt_const_args += " -full";
opt_expr_args += " -full";
continue;
}
break;
@ -158,8 +158,8 @@ struct Ice40OptPass : public Pass {
for (auto module : design->selected_modules())
run_ice40_opts(module);
Pass::call(design, "opt_const " + opt_const_args);
Pass::call(design, "opt_share");
Pass::call(design, "opt_expr " + opt_expr_args);
Pass::call(design, "opt_merge");
Pass::call(design, "opt_rmdff");
Pass::call(design, "opt_clean");

271
techlibs/ice40/synth_ice40.cc
View file

@ -25,18 +25,11 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
struct SynthIce40Pass : public ScriptPass
{
if (label == run_from)
active = true;
if (label == run_to)
active = false;
return active;
}
SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
struct SynthIce40Pass : public Pass {
SynthIce40Pass() : Pass("synth_ice40", "synthesis for iCE40 FPGAs") { }
virtual void help()
virtual void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@ -77,73 +70,30 @@ struct SynthIce40Pass : public Pass {
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
log("\n");
log(" begin:\n");
log(" read_verilog -lib +/ice40/cells_sim.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (unless -noflatten)\n");
log(" proc\n");
log(" flatten\n");
log(" tribuf -logic\n");
log("\n");
log(" coarse:\n");
log(" synth -run coarse\n");
log("\n");
log(" bram: (skip if -nobram)\n");
log(" memory_bram -rules +/ice40/brams.txt\n");
log(" techmap -map +/ice40/brams_map.v\n");
log("\n");
log(" fine:\n");
log(" opt -fast -mux_undef -undriven -fine\n");
log(" memory_map\n");
log(" opt -undriven -fine\n");
log(" techmap -map +/techmap.v [-map +/ice40/arith_map.v]\n");
log(" abc -dff (only if -retime)\n");
log(" ice40_opt\n");
log("\n");
log(" map_ffs:\n");
log(" dffsr2dff\n");
log(" dff2dffe -direct-match $_DFF_*\n");
log(" techmap -map +/ice40/cells_map.v\n");
log(" opt_const -mux_undef\n");
log(" simplemap\n");
log(" ice40_ffinit\n");
log(" ice40_ffssr\n");
log(" ice40_opt -full\n");
log("\n");
log(" map_luts:\n");
log(" abc (only if -abc2)\n");
log(" ice40_opt (only if -abc2)\n");
log(" abc -lut 4\n");
log(" clean\n");
log("\n");
log(" map_cells:\n");
log(" techmap -map +/ice40/cells_map.v\n");
log(" clean\n");
log("\n");
log(" check:\n");
log(" hierarchy -check\n");
log(" stat\n");
log(" check -noinit\n");
log("\n");
log(" blif:\n");
log(" write_blif -gates -attr -param <file-name>\n");
log("\n");
log(" edif:\n");
log(" write_edif <file-name>\n");
help_script();
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
string top_opt = "-auto-top";
string blif_file, edif_file;
bool nocarry, nobram, flatten, retime, abc2;
virtual void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
blif_file = "";
edif_file = "";
nocarry = false;
nobram = false;
flatten = true;
retime = false;
abc2 = false;
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
std::string top_opt = "-auto-top";
std::string run_from, run_to;
std::string blif_file, edif_file;
bool nocarry = false;
bool nobram = false;
bool flatten = true;
bool retime = false;
bool abc2 = false;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -199,98 +149,101 @@ struct SynthIce40Pass : public Pass {
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
bool active = run_from.empty();
log_header("Executing SYNTH_ICE40 pass.\n");
log_push();
if (check_label(active, run_from, run_to, "begin"))
{
Pass::call(design, "read_verilog -lib +/ice40/cells_sim.v");
Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
}
if (flatten && check_label(active, run_from, run_to, "flatten"))
{
Pass::call(design, "proc");
Pass::call(design, "flatten");
Pass::call(design, "tribuf -logic");
}
if (check_label(active, run_from, run_to, "coarse"))
{
Pass::call(design, "synth -run coarse");
}
if (!nobram && check_label(active, run_from, run_to, "bram"))
{
Pass::call(design, "memory_bram -rules +/ice40/brams.txt");
Pass::call(design, "techmap -map +/ice40/brams_map.v");
}
if (check_label(active, run_from, run_to, "fine"))
{
Pass::call(design, "opt -fast -mux_undef -undriven -fine");
Pass::call(design, "memory_map");
Pass::call(design, "opt -undriven -fine");
if (nocarry)
Pass::call(design, "techmap");
else
Pass::call(design, "techmap -map +/techmap.v -map +/ice40/arith_map.v");
if (retime)
Pass::call(design, "abc -dff");
Pass::call(design, "ice40_opt");
}
if (check_label(active, run_from, run_to, "map_ffs"))
{
Pass::call(design, "dffsr2dff");
Pass::call(design, "dff2dffe -direct-match $_DFF_*");
Pass::call(design, "techmap -map +/ice40/cells_map.v");
Pass::call(design, "opt_const -mux_undef");
Pass::call(design, "simplemap");
Pass::call(design, "ice40_ffinit");
Pass::call(design, "ice40_ffssr");
Pass::call(design, "ice40_opt -full");
}
if (check_label(active, run_from, run_to, "map_luts"))
{
if (abc2) {
Pass::call(design, "abc");
Pass::call(design, "ice40_opt");
}
Pass::call(design, "abc -lut 4");
Pass::call(design, "clean");
}
if (check_label(active, run_from, run_to, "map_cells"))
{
Pass::call(design, "techmap -map +/ice40/cells_map.v");
Pass::call(design, "clean");
}
if (check_label(active, run_from, run_to, "check"))
{
Pass::call(design, "hierarchy -check");
Pass::call(design, "stat");
Pass::call(design, "check -noinit");
}
if (check_label(active, run_from, run_to, "blif"))
{
if (!blif_file.empty())
Pass::call(design, stringf("write_blif -gates -attr -param %s", blif_file.c_str()));
}
if (check_label(active, run_from, run_to, "edif"))
{
if (!edif_file.empty())
Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
}
run_script(design, run_from, run_to);
log_pop();
}
virtual void script() YS_OVERRIDE
{
if (check_label("begin"))
{
run("read_verilog -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc");
run("flatten");
run("tribuf -logic");
}
if (check_label("coarse"))
{
run("synth -run coarse");
}
if (!nobram && check_label("bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/ice40/brams.txt");
run("techmap -map +/ice40/brams_map.v");
}
if (check_label("fine"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
if (nocarry)
run("techmap");
else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("ice40_opt");
}
if (check_label("map_ffs"))
{
run("dffsr2dff");
run("dff2dffe -direct-match $_DFF_*");
run("techmap -map +/ice40/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("ice40_ffinit");
run("ice40_ffssr");
run("ice40_opt -full");
}
if (check_label("map_luts"))
{
if (abc2 || help_mode) {
run("abc", " (only if -abc2)");
run("ice40_opt", "(only if -abc2)");
}
run("abc -lut 4");
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/ice40/cells_map.v");
run("clean");
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat");
run("check -noinit");
}
if (check_label("blif"))
{
if (!blif_file.empty() || help_mode)
run(stringf("write_blif -gates -attr -param %s", help_mode ? "<file-name>" : blif_file.c_str()));
}
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
}
}
} SynthIce40Pass;
PRIVATE_NAMESPACE_END