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Revert "verilog: fix string literal regular expression (#5187)"

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This reverts commit 834a7294b7.
This commit is contained in:
Emil J. Tywoniak 2025-07-10 21:15:38 +02:00
parent 36491569d2
commit f27309136f
2 changed files with 1 additions and 6 deletions
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5
tests/verilog/bug5160.v
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@ -1,5 +0,0 @@
// Regression test for bug mentioned in #5160:
// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
module top;
initial $display( "\\" );
endmodule