mirror of
https://github.com/YosysHQ/yosys
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smt2: Use Mem helper.
This commit is contained in:
Marcelina Kościelnicka
parent
ec483b7c3b
commit
f272c8b407
1 changed files with 253 additions and 195 deletions
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@ -22,6 +22,7 @@
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/mem.h"
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#include <string>
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USING_YOSYS_NAMESPACE
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@ -40,12 +41,15 @@ struct Smt2Worker
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std::map<RTLIL::SigBit, RTLIL::Cell*> bit_driver;
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std::set<RTLIL::Cell*> exported_cells, hiercells, hiercells_queue;
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pool<Cell*> recursive_cells, registers;
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std::vector<Mem> memories;
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dict<Cell*, Mem*> mem_cells;
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std::set<Mem*> memory_queue;
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pool<SigBit> clock_posedge, clock_negedge;
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vector<string> ex_state_eq, ex_input_eq;
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std::map<RTLIL::SigBit, std::pair<int, int>> fcache;
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std::map<Cell*, int> memarrays;
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std::map<Mem*, int> memarrays;
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std::map<int, int> bvsizes;
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dict<IdString, char*> ids;
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@ -116,12 +120,73 @@ struct Smt2Worker
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makebits(stringf("%s_is", get_id(module)));
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dict<IdString, Mem*> mem_dict;
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memories = Mem::get_all_memories(module);
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for (auto &mem : memories)
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{
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mem_dict[mem.memid] = &mem;
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for (auto &port : mem.wr_ports)
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{
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if (port.clk_enable) {
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SigSpec clk = sigmap(port.clk);
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for (int i = 0; i < GetSize(clk); i++)
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{
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if (clk[i].wire == nullptr)
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continue;
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if (port.clk_polarity)
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clock_posedge.insert(clk[i]);
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else
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clock_negedge.insert(clk[i]);
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}
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}
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for (auto bit : sigmap(port.en))
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noclock.insert(bit);
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for (auto bit : sigmap(port.addr))
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noclock.insert(bit);
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for (auto bit : sigmap(port.data))
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noclock.insert(bit);
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}
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for (auto &port : mem.rd_ports)
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{
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if (port.clk_enable) {
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SigSpec clk = sigmap(port.clk);
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for (int i = 0; i < GetSize(clk); i++)
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{
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if (clk[i].wire == nullptr)
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continue;
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if (port.clk_polarity)
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clock_posedge.insert(clk[i]);
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else
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clock_negedge.insert(clk[i]);
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}
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}
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for (auto bit : sigmap(port.en))
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noclock.insert(bit);
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for (auto bit : sigmap(port.addr))
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noclock.insert(bit);
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for (auto bit : sigmap(port.data))
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noclock.insert(bit);
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Cell *driver = port.cell ? port.cell : mem.cell;
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for (auto bit : sigmap(port.data)) {
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if (bit_driver.count(bit))
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log_error("Found multiple drivers for %s.\n", log_signal(bit));
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bit_driver[bit] = driver;
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}
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}
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}
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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{
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if (GetSize(conn.second) == 0)
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continue;
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// Handled above.
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if (cell->type.in(ID($mem), ID($memrd), ID($memwr), ID($meminit))) {
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mem_cells[cell] = mem_dict[cell->parameters.at(ID::MEMID).decode_string()];
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continue;
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}
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bool is_input = ct.cell_input(cell->type, conn.first);
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bool is_output = ct.cell_output(cell->type, conn.first);
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@ -135,24 +200,6 @@ struct Smt2Worker
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log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
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log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type));
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if (cell->type.in(ID($mem)) && conn.first.in(ID::RD_CLK, ID::WR_CLK))
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{
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SigSpec clk = sigmap(conn.second);
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for (int i = 0; i < GetSize(clk); i++)
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{
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if (clk[i].wire == nullptr)
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continue;
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if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_ENABLE : ID::WR_CLK_ENABLE)[i] != State::S1)
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continue;
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if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_POLARITY : ID::WR_CLK_POLARITY)[i] == State::S1)
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clock_posedge.insert(clk[i]);
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else
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clock_negedge.insert(clk[i]);
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}
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}
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else
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if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && conn.first.in(ID::CLK, ID::C))
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{
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bool posedge = (cell->type == ID($_DFF_N_)) || (cell->type == ID($dff) && cell->getParam(ID::CLK_POLARITY).as_bool());
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@ -647,27 +694,35 @@ struct Smt2Worker
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// FIXME: $slice $concat
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}
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if (memmode && cell->type == ID($mem))
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if (memmode && cell->type.in(ID($mem), ID($memrd), ID($memwr), ID($meminit)))
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{
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int arrayid = idcounter++;
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memarrays[cell] = arrayid;
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Mem *mem = mem_cells[cell];
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
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int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
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bool async_read = false;
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if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) {
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if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero())
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log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module));
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async_read = true;
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if (memarrays.count(mem)) {
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recursive_cells.erase(cell);
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return;
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}
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decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", get_id(cell), abits, width, rd_ports, wr_ports, async_read ? "async" : "sync"));
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int arrayid = idcounter++;
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memarrays[mem] = arrayid;
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int abits = ceil_log2(mem->size);
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bool has_sync_wr = false;
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bool has_async_wr = false;
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for (auto &port : mem->wr_ports) {
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if (port.clk_enable)
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has_sync_wr = true;
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else
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has_async_wr = true;
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}
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if (has_async_wr && has_sync_wr)
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log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module));
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decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", get_id(mem->memid), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
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string memstate;
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if (async_read) {
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if (has_async_wr) {
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memstate = stringf("%s#%d#final", get_id(module), arrayid);
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} else {
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memstate = stringf("%s#%d#0", get_id(module), arrayid);
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@ -675,80 +730,79 @@ struct Smt2Worker
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if (statebv)
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{
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int mem_size = cell->getParam(ID::SIZE).as_int();
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int mem_offset = cell->getParam(ID::OFFSET).as_int();
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makebits(memstate, width*mem_size, get_id(cell));
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makebits(memstate, mem->width*mem->size, get_id(mem->memid));
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decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n",
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get_id(module), get_id(cell), get_id(module), width*mem_size, memstate.c_str()));
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get_id(module), get_id(mem->memid), get_id(module), mem->width*mem->size, memstate.c_str()));
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for (int i = 0; i < rd_ports; i++)
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for (int i = 0; i < GetSize(mem->rd_ports); i++)
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{
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SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits);
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SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width);
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auto &port = mem->rd_ports[i];
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SigSpec addr_sig = port.addr;
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addr_sig.extend_u0(abits);
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std::string addr = get_bv(addr_sig);
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if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
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if (port.clk_enable)
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log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), log_id(mem->memid), log_id(module));
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decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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std::string read_expr = "#b";
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for (int k = 0; k < width; k++)
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for (int k = 0; k < mem->width; k++)
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read_expr += "0";
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for (int k = 0; k < mem_size; k++)
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for (int k = 0; k < mem->size; k++)
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read_expr = stringf("(ite (= (|%s_m:R%dA %s| state) #b%s) ((_ extract %d %d) (|%s| state))\n %s)",
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get_id(module), i, get_id(cell), Const(k+mem_offset, abits).as_string().c_str(),
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width*(k+1)-1, width*k, memstate.c_str(), read_expr.c_str());
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get_id(module), i, get_id(mem->memid), Const(k+mem->start_offset, abits).as_string().c_str(),
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mem->width*(k+1)-1, mem->width*k, memstate.c_str(), read_expr.c_str());
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d)\n %s) ; %s\n",
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get_id(module), idcounter, get_id(module), width, read_expr.c_str(), log_signal(data_sig)));
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get_id(module), idcounter, get_id(module), mem->width, read_expr.c_str(), log_signal(port.data)));
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decls.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
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get_id(module), i, get_id(mem->memid), get_id(module), mem->width, get_id(module), idcounter));
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register_bv(data_sig, idcounter++);
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register_bv(port.data, idcounter++);
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}
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}
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else
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{
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if (statedt)
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dtmembers.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
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memstate.c_str(), abits, width, get_id(cell)));
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memstate.c_str(), abits, mem->width, get_id(mem->memid)));
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else
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decls.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
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memstate.c_str(), get_id(module), abits, width, get_id(cell)));
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memstate.c_str(), get_id(module), abits, mem->width, get_id(mem->memid)));
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decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s| state))\n",
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get_id(module), get_id(cell), get_id(module), abits, width, memstate.c_str()));
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get_id(module), get_id(mem->memid), get_id(module), abits, mem->width, memstate.c_str()));
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for (int i = 0; i < rd_ports; i++)
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for (int i = 0; i < GetSize(mem->rd_ports); i++)
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{
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SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits);
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SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width);
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auto &port = mem->rd_ports[i];
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SigSpec addr_sig = port.addr;
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addr_sig.extend_u0(abits);
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std::string addr = get_bv(addr_sig);
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if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
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if (port.clk_enable)
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log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), log_id(mem->memid), log_id(module));
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decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s| state) (|%s_m:R%dA %s| state))) ; %s\n",
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get_id(module), idcounter, get_id(module), width, memstate.c_str(), get_id(module), i, get_id(cell), log_signal(data_sig)));
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get_id(module), idcounter, get_id(module), mem->width, memstate.c_str(), get_id(module), i, get_id(mem->memid), log_signal(port.data)));
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decls.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
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get_id(module), i, get_id(mem->memid), get_id(module), mem->width, get_id(module), idcounter));
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register_bv(data_sig, idcounter++);
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register_bv(port.data, idcounter++);
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}
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}
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registers.insert(cell);
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memory_queue.insert(mem);
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recursive_cells.erase(cell);
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return;
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}
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@ -977,7 +1031,7 @@ struct Smt2Worker
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}
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}
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for (int iter = 1; !registers.empty(); iter++)
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for (int iter = 1; !registers.empty() || !memory_queue.empty(); iter++)
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{
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pool<Cell*> this_regs;
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this_regs.swap(registers);
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@ -1010,130 +1064,135 @@ struct Smt2Worker
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if (cell->type == ID($anyconst))
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ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str()));
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}
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}
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if (cell->type == ID($mem))
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std::set<Mem*> this_mems;
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this_mems.swap(memory_queue);
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for (auto mem : this_mems)
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{
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int arrayid = memarrays.at(cell);
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int arrayid = memarrays.at(mem);
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
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int abits = ceil_log2(mem->size);;
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bool has_sync_wr = false;
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bool has_async_wr = false;
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for (auto &port : mem->wr_ports) {
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if (port.clk_enable)
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has_sync_wr = true;
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else
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has_async_wr = true;
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}
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bool async_read = false;
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string initial_memstate, final_memstate;
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if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) {
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log_assert(cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero());
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async_read = true;
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if (has_async_wr) {
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log_assert(!has_sync_wr);
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initial_memstate = stringf("%s#%d#0", get_id(module), arrayid);
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final_memstate = stringf("%s#%d#final", get_id(module), arrayid);
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}
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if (statebv)
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{
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int mem_size = cell->getParam(ID::SIZE).as_int();
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int mem_offset = cell->getParam(ID::OFFSET).as_int();
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if (async_read) {
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makebits(final_memstate, width*mem_size, get_id(cell));
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if (has_async_wr) {
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makebits(final_memstate, mem->width*mem->size, get_id(mem->memid));
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}
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for (int i = 0; i < wr_ports; i++)
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for (int i = 0; i < GetSize(mem->wr_ports); i++)
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{
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SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits);
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SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width);
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SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width);
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auto &port = mem->wr_ports[i];
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SigSpec addr_sig = port.addr;
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addr_sig.extend_u0(abits);
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std::string addr = get_bv(addr_sig);
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std::string data = get_bv(data_sig);
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std::string mask = get_bv(mask_sig);
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std::string data = get_bv(port.data);
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std::string mask = get_bv(port.en);
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|
||||
decls.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
|
||||
get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
|
||||
addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(cell));
|
||||
get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
|
||||
addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(mem->memid));
|
||||
|
||||
decls.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
|
||||
get_id(module), i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
|
||||
data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(cell));
|
||||
get_id(module), i, get_id(mem->memid), get_id(module), mem->width, data.c_str(), log_signal(port.data)));
|
||||
data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(mem->memid));
|
||||
|
||||
decls.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
|
||||
get_id(module), i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
|
||||
mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(cell));
|
||||
get_id(module), i, get_id(mem->memid), get_id(module), mem->width, mask.c_str(), log_signal(port.en)));
|
||||
mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(mem->memid));
|
||||
|
||||
std::string data_expr;
|
||||
|
||||
for (int k = mem_size-1; k >= 0; k--) {
|
||||
for (int k = mem->size-1; k >= 0; k--) {
|
||||
std::string new_data = stringf("(bvor (bvand %s %s) (bvand ((_ extract %d %d) (|%s#%d#%d| state)) (bvnot %s)))",
|
||||
data.c_str(), mask.c_str(), width*(k+1)-1, width*k, get_id(module), arrayid, i, mask.c_str());
|
||||
data.c_str(), mask.c_str(), mem->width*(k+1)-1, mem->width*k, get_id(module), arrayid, i, mask.c_str());
|
||||
data_expr += stringf("\n (ite (= %s #b%s) %s ((_ extract %d %d) (|%s#%d#%d| state)))",
|
||||
addr.c_str(), Const(k+mem_offset, abits).as_string().c_str(), new_data.c_str(),
|
||||
width*(k+1)-1, width*k, get_id(module), arrayid, i);
|
||||
addr.c_str(), Const(k+mem->start_offset, abits).as_string().c_str(), new_data.c_str(),
|
||||
mem->width*(k+1)-1, mem->width*k, get_id(module), arrayid, i);
|
||||
}
|
||||
|
||||
decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (_ BitVec %d) (concat%s)) ; %s\n",
|
||||
get_id(module), arrayid, i+1, get_id(module), width*mem_size, data_expr.c_str(), get_id(cell)));
|
||||
get_id(module), arrayid, i+1, get_id(module), mem->width*mem->size, data_expr.c_str(), get_id(mem->memid)));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (async_read) {
|
||||
if (has_async_wr) {
|
||||
if (statedt)
|
||||
dtmembers.push_back(stringf(" (|%s| (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
|
||||
initial_memstate.c_str(), abits, width, get_id(cell)));
|
||||
initial_memstate.c_str(), abits, mem->width, get_id(mem->memid)));
|
||||
else
|
||||
decls.push_back(stringf("(declare-fun |%s| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
|
||||
initial_memstate.c_str(), get_id(module), abits, width, get_id(cell)));
|
||||
initial_memstate.c_str(), get_id(module), abits, mem->width, get_id(mem->memid)));
|
||||
}
|
||||
|
||||
for (int i = 0; i < wr_ports; i++)
|
||||
for (int i = 0; i < GetSize(mem->wr_ports); i++)
|
||||
{
|
||||
SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits);
|
||||
SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width);
|
||||
SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width);
|
||||
auto &port = mem->wr_ports[i];
|
||||
SigSpec addr_sig = port.addr;
|
||||
addr_sig.extend_u0(abits);
|
||||
|
||||
std::string addr = get_bv(addr_sig);
|
||||
std::string data = get_bv(data_sig);
|
||||
std::string mask = get_bv(mask_sig);
|
||||
std::string data = get_bv(port.data);
|
||||
std::string mask = get_bv(port.en);
|
||||
|
||||
decls.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
|
||||
get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
|
||||
addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(cell));
|
||||
get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
|
||||
addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(mem->memid));
|
||||
|
||||
decls.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
|
||||
get_id(module), i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
|
||||
data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(cell));
|
||||
get_id(module), i, get_id(mem->memid), get_id(module), mem->width, data.c_str(), log_signal(port.data)));
|
||||
data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(mem->memid));
|
||||
|
||||
decls.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
|
||||
get_id(module), i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
|
||||
mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(cell));
|
||||
get_id(module), i, get_id(mem->memid), get_id(module), mem->width, mask.c_str(), log_signal(port.en)));
|
||||
mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(mem->memid));
|
||||
|
||||
data = stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
|
||||
data.c_str(), mask.c_str(), get_id(module), arrayid, i, addr.c_str(), mask.c_str());
|
||||
|
||||
decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
|
||||
"(store (|%s#%d#%d| state) %s %s)) ; %s\n",
|
||||
get_id(module), arrayid, i+1, get_id(module), abits, width,
|
||||
get_id(module), arrayid, i, addr.c_str(), data.c_str(), get_id(cell)));
|
||||
get_id(module), arrayid, i+1, get_id(module), abits, mem->width,
|
||||
get_id(module), arrayid, i, addr.c_str(), data.c_str(), get_id(mem->memid)));
|
||||
}
|
||||
}
|
||||
|
||||
std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, wr_ports);
|
||||
std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, GetSize(mem->wr_ports));
|
||||
std::string expr_q = stringf("(|%s#%d#0| next_state)", get_id(module), arrayid);
|
||||
trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell)));
|
||||
trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d.c_str(), expr_q.c_str(), get_id(mem->memid)));
|
||||
ex_state_eq.push_back(stringf("(= (|%s#%d#0| state) (|%s#%d#0| other_state))", get_id(module), arrayid, get_id(module), arrayid));
|
||||
|
||||
if (async_read)
|
||||
hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(cell)));
|
||||
if (has_async_wr)
|
||||
hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(mem->memid)));
|
||||
|
||||
Const init_data = cell->getParam(ID::INIT);
|
||||
int memsize = cell->getParam(ID::SIZE).as_int();
|
||||
Const init_data = mem->get_init_data();
|
||||
|
||||
for (int i = 0; i < memsize; i++)
|
||||
for (int i = 0; i < mem->size; i++)
|
||||
{
|
||||
if (i*width >= GetSize(init_data))
|
||||
if (i*mem->width >= GetSize(init_data))
|
||||
break;
|
||||
|
||||
Const initword = init_data.extract(i*width, width, State::Sx);
|
||||
Const initword = init_data.extract(i*mem->width, mem->width, State::Sx);
|
||||
Const initmask = initword;
|
||||
bool gen_init_constr = false;
|
||||
|
||||
|
|
@ -1154,8 +1213,7 @@ struct Smt2Worker
|
|||
else
|
||||
init_list.push_back(stringf("(= (bvand (select (|%s#%d#0| state) #b%s) #b%s) #b%s) ; %s[%d]",
|
||||
get_id(module), arrayid, Const(i, abits).as_string().c_str(),
|
||||
initmask.as_string().c_str(), initword.as_string().c_str(), get_id(cell), i));
|
||||
}
|
||||
initmask.as_string().c_str(), initword.as_string().c_str(), get_id(mem->memid), i));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1586,7 +1644,7 @@ struct Smt2Backend : public Backend {
|
|||
|
||||
for (auto module : sorted_modules)
|
||||
{
|
||||
if (module->get_blackbox_attribute() || module->has_memories_warn() || module->has_processes_warn())
|
||||
if (module->get_blackbox_attribute() || module->has_processes_warn())
|
||||
continue;
|
||||
|
||||
log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue