mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

log_debug() for abc9_{arrival,required} times

Browse source
This commit is contained in:
Eddie Hung 2020-01-10 17:13:27 -08:00
parent 28f814ee59
commit f24de88f38
2 changed files with 15 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/techmap/abc9_ops.cc
View file

@ -512,7 +512,7 @@ void prep_times(RTLIL::Design *design)
requireds.clear();
for (auto cell : boxes) {
RTLIL::Module* inst_module = module->design->module(cell->type);
log_assert(inst_module);
for (auto &conn : cell->connections_) {
auto port_wire = inst_module->wire(conn.first);
if (!port_wire->port_input)
@ -537,6 +537,12 @@ void prep_times(RTLIL::Design *design)
SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
for (const auto &i : requireds) {
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), i.first);
}
#endif
delays.insert(i.first);
for (auto offset : i.second) {
auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));