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Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
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commit
f24bc1ed0a
11 changed files with 649 additions and 21 deletions
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@ -71,7 +71,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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if (stage == 0)
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{
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log_assert(type == AST_MODULE);
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log_assert(type == AST_MODULE || type == AST_INTERFACE);
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last_blocking_assignment_warn = pair<string, int>();
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deep_recursion_warning = true;
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