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Merge pull request #659 from rubund/sv_interfaces

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Support for SystemVerilog interfaces and modports
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Clifford Wolf 2018-10-18 10:58:47 +02:00 • committed by GitHub
commit f24bc1ed0a
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11 changed files with 649 additions and 21 deletions
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frontends/ast/simplify.cc
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@ -71,7 +71,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (stage == 0)
{
log_assert(type == AST_MODULE);
log_assert(type == AST_MODULE || type == AST_INTERFACE);
last_blocking_assignment_warn = pair<string, int>();
deep_recursion_warning = true;