3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 10:05:33 +00:00

Merge pull request #659 from rubund/sv_interfaces

Support for SystemVerilog interfaces and modports
This commit is contained in:
Clifford Wolf 2018-10-18 10:58:47 +02:00 committed by GitHub
commit f24bc1ed0a
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
11 changed files with 649 additions and 21 deletions

View file

@ -452,6 +452,9 @@ from SystemVerilog:
into a design with ``read_verilog``, all its packages are available to
SystemVerilog files being read into the same design afterwards.
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
Building the documentation
==========================