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Merge branch 'master' into master

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Sergey 2019-08-30 10:29:47 +03:00 • committed by GitHub
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6 changed files with 51 additions and 27 deletions
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8
techlibs/ice40/abc_hx.box
View file

@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically # NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out) # (with exceptions for carry in/out)
# Inputs: A B CI # Inputs: A B I0 I3 CI
# Outputs: O CO # Outputs: O CO
# (NB: carry chain input/output must be last # (NB: carry chain input/output must be last
# input/output and have been moved there # input/output and have been moved there
# overriding the alphabetical ordering) # overriding the alphabetical ordering)
$__ICE40_FULL_ADDER 1 1 3 2 $__ICE40_CARRY_WRAPPER 1 1 5 2
400 379 316 400 379 449 316 316
259 231 126 259 231 - - 126

8
techlibs/ice40/abc_lp.box
View file

@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically # NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out) # (with exceptions for carry in/out)
# Inputs: A B CI # Inputs: A B I0 I3 CI
# Outputs: O CO # Outputs: O CO
# (NB: carry chain input/output must be last # (NB: carry chain input/output must be last
# input/output and have been moved there # input/output and have been moved there
# overriding the alphabetical ordering) # overriding the alphabetical ordering)
$__ICE40_FULL_ADDER 1 1 3 2 $__ICE40_CARRY_WRAPPER 1 1 5 2
589 558 465 589 558 661 465 465
675 609 186 675 609 - - 186

8
techlibs/ice40/abc_u.box
View file

@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically # NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out) # (with exceptions for carry in/out)
# Inputs: A B CI # Inputs: A B I0 I3 CI
# Outputs: O CO # Outputs: O CO
# (NB: carry chain input/output must be last # (NB: carry chain input/output must be last
# input/output and have been moved there # input/output and have been moved there
# overriding the alphabetical ordering) # overriding the alphabetical ordering)
$__ICE40_FULL_ADDER 1 1 3 2 $__ICE40_CARRY_WRAPPER 1 1 5 2
1231 1205 874 1231 1205 1285 874 874
675 609 278 675 609 - - 278

19
techlibs/ice40/cells_sim.v
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@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
endmodule endmodule
(* abc_box_id = 1, lib_whitebox *) (* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER ( module \$__ICE40_CARRY_WRAPPER (
(* abc_carry *) (* abc_carry *)
output CO, output CO,
output O, output O,
input A, input A, B,
input B,
(* abc_carry *) (* abc_carry *)
input CI input CI,
input I0, I3
); );
parameter LUT = 0;
SB_CARRY carry ( SB_CARRY carry (
.I0(A), .I0(A),
.I1(B), .I1(B),
@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER (
.CO(CO) .CO(CO)
); );
SB_LUT4 #( SB_LUT4 #(
// I0: 1010 1010 1010 1010 .LUT_INIT(LUT)
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder ( ) adder (
.I0(1'b0), .I0(I0),
.I1(A), .I1(A),
.I2(B), .I2(B),
.I3(CI), .I3(I3),
.O(O) .O(O)
); );
endmodule endmodule

9
techlibs/ice40/ice40_opt.cc
View file

@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
continue; continue;
} }
if (cell->type == "$__ICE40_FULL_ADDER") if (cell->type == "$__ICE40_CARRY_WRAPPER")
{ {
SigSpec non_const_inputs, replacement_output; SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0; int count_zeros = 0, count_ones = 0;
@ -114,16 +114,17 @@ static void run_ice40_opts(Module *module)
optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output); module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true); module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output)); log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut"; cell->type = "$lut";
cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
cell->setPort("\\Y", cell->getPort("\\O")); cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B"); cell->unsetPort("\\B");
cell->unsetPort("\\CI"); cell->unsetPort("\\CI");
cell->unsetPort("\\I0");
cell->unsetPort("\\I3");
cell->unsetPort("\\CO"); cell->unsetPort("\\CO");
cell->unsetPort("\\O"); cell->unsetPort("\\O");
cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
cell->setParam("\\WIDTH", 4); cell->setParam("\\WIDTH", 4);
} }
continue; continue;

26
tests/ice40/ice40_opt.ys Normal file
View file

@ -0,0 +1,26 @@
read_verilog -icells -formal <<EOT
module top(input CI, I0, output [1:0] CO, output O);
wire A = 1'b0, B = 1'b0;
\$__ICE40_CARRY_WRAPPER #(
// A[0]: 1010 1010 1010 1010
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
.LUT(~16'b 0110_1001_1001_0110)
) u0 (
.A(A),
.B(B),
.CI(CI),
.I0(I0),
.I3(CI),
.CO(CO[0]),
.O(O)
);
SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
endmodule
EOT
equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:$lut