mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Replace std::set with pool for cell_to_inbit and outbit_to_cell.

Browse source
This commit is contained in:
Alberto Gonzalez 2020-04-20 04:46:09 +00:00
parent 6294621825
commit f235f212ea
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
passes/techmap/techmap.cc
View file

@ -490,8 +490,8 @@ struct TechmapWorker
} }
TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells; TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit; dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell; dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {