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xilinx: fix IdString memory leak

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This commit is contained in:
Emil J. Tywoniak 2025-11-13 12:42:06 +01:00
parent a915143768
commit f2263642a4
1 changed files with 14 additions and 14 deletions
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28
techlibs/xilinx/xilinx_dsp_cascade.pmg
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@ -90,9 +90,9 @@ finally
if (i % MAX_DSP_CASCADE > 0) { if (i % MAX_DSP_CASCADE > 0) {
if (P >= 0) { if (P >= 0) {
Wire *cascade = module->addWire(NEW_ID, 48); Wire *cascade = module->addWire(NEW_ID, 48);
dsp_pcin->setPort(ID(C), Const(0, 48)); dsp_pcin->setPort(\C, Const(0, 48));
dsp_pcin->setPort(ID(PCIN), cascade); dsp_pcin->setPort(\PCIN, cascade);
dsp->setPort(ID(PCOUT), cascade); dsp->setPort(\PCOUT, cascade);
add_siguser(cascade, dsp_pcin); add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp); add_siguser(cascade, dsp);
@ -118,15 +118,15 @@ finally
} }
if (AREG >= 0) { if (AREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 30); Wire *cascade = module->addWire(NEW_ID, 30);
dsp_pcin->setPort(ID(A), Const(0, 30)); dsp_pcin->setPort(\A, Const(0, 30));
dsp_pcin->setPort(ID(ACIN), cascade); dsp_pcin->setPort(\ACIN, cascade);
dsp->setPort(ID(ACOUT), cascade); dsp->setPort(\ACOUT, cascade);
add_siguser(cascade, dsp_pcin); add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp); add_siguser(cascade, dsp);
if (dsp->type.in(\DSP48E1)) if (dsp->type.in(\DSP48E1))
dsp->setParam(ID(ACASCREG), AREG); dsp->setParam(\ACASCREG, AREG);
dsp_pcin->setParam(ID(A_INPUT), Const("CASCADE")); dsp_pcin->setParam(\A_INPUT, Const("CASCADE"));
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
} }
@ -138,18 +138,18 @@ finally
// BCOUT from an adjacent DSP48A1 slice. The tools then // BCOUT from an adjacent DSP48A1 slice. The tools then
// translate BCOUT cascading to the dedicated BCIN input // translate BCOUT cascading to the dedicated BCIN input
// and set the B_INPUT attribute for implementation." // and set the B_INPUT attribute for implementation."
dsp_pcin->setPort(ID(B), cascade); dsp_pcin->setPort(\B, cascade);
} }
else { else {
dsp_pcin->setPort(ID(B), Const(0, 18)); dsp_pcin->setPort(\B, Const(0, 18));
dsp_pcin->setPort(ID(BCIN), cascade); dsp_pcin->setPort(\BCIN, cascade);
} }
dsp->setPort(ID(BCOUT), cascade); dsp->setPort(\BCOUT, cascade);
add_siguser(cascade, dsp_pcin); add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp); add_siguser(cascade, dsp);
if (dsp->type.in(\DSP48E1)) { if (dsp->type.in(\DSP48E1)) {
dsp->setParam(ID(BCASCREG), BREG); dsp->setParam(\BCASCREG, BREG);
// According to UG389 p13 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf] // According to UG389 p13 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
// "The attribute is only used by place and route tools and // "The attribute is only used by place and route tools and
// is not necessary for the users to set for synthesis. The // is not necessary for the users to set for synthesis. The
@ -158,7 +158,7 @@ finally
// BCOUT of another DSP48A1 slice, then the tools automatically // BCOUT of another DSP48A1 slice, then the tools automatically
// set the attribute to 'CASCADE', otherwise it is set to // set the attribute to 'CASCADE', otherwise it is set to
// 'DIRECT'". // 'DIRECT'".
dsp_pcin->setParam(ID(B_INPUT), Const("CASCADE")); dsp_pcin->setParam(\B_INPUT, Const("CASCADE"));
} }
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));