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Merge pull request #1888 from boqwxp/cleanup_scatter

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Clean up `passes/cmds/scatter.cc`.
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whitequark 2020-04-17 02:21:23 +00:00 committed by GitHub
parent 5c428996a9 ff8be2364e
commit f2064c8131
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1 changed files with 11 additions and 17 deletions
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28
passes/cmds/scatter.cc
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@ -46,25 +46,19 @@ struct ScatterPass : public Pass {
CellTypes ct(design); CellTypes ct(design);
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) for (auto module : design->selected_modules())
{ {
if (!design->selected(mod_it.second)) for (auto cell : module->cells()) {
continue; dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
for (auto conn : cell->connections())
for (auto &c : mod_it.second->cells_) new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
for (auto &p : c.second->connections_) for (auto &it : new_connections) {
{ if (ct.cell_output(cell->type, it.first))
RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size()); module->connect(RTLIL::SigSig(it.second.first, it.second.second));
else
if (ct.cell_output(c.second->type, p.first)) { module->connect(RTLIL::SigSig(it.second.second, it.second.first));
RTLIL::SigSig sigsig(p.second, wire); cell->setPort(it.first, it.second.second);
mod_it.second->connect(sigsig);
} else {
RTLIL::SigSig sigsig(wire, p.second);
mod_it.second->connect(sigsig);
} }
p.second = wire;
} }
} }
} }