mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Refactor into AigerReader class

Browse source
This commit is contained in:
Eddie Hung 2019-02-08 12:04:26 -08:00
parent 2a8cc36578
commit f1befe1b44
2 changed files with 94 additions and 81 deletions
Download patch file Download diff file Expand all files Collapse all files

21
frontends/aiger/aigerparse.h
View file

@ -24,7 +24,26 @@
YOSYS_NAMESPACE_BEGIN
extern void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
struct AigerReader
{
RTLIL::Design *design;
std::istream &f;
std::string clk_name;
RTLIL::Module *module;
unsigned M, I, L, O, A;
unsigned B, C, J, F; // Optional in AIGER 1.9
unsigned line_count;
std::vector<RTLIL::Wire*> inputs;
std::vector<RTLIL::Wire*> latches;
std::vector<RTLIL::Wire*> outputs;
AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
void parse_aiger();
void parse_aiger_ascii();
void parse_aiger_binary();
};
YOSYS_NAMESPACE_END